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* scc to use design->selected_modules() which avoids black/white-boxesEddie Hung2020-01-071-26/+25
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Implemented "scc -set_attr"Clifford Wolf2016-11-061-22/+32
* Bugfix in "scc" commandClifford Wolf2016-11-061-9/+11
* Fixed "scc" for cells that have feedback singals _and_ are part of a larger loopClifford Wolf2016-05-271-3/+3
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Import more std:: stuff into Yosys namespaceClifford Wolf2015-10-251-2/+2
* Some ASCII encoding fixes (comments and docs) by Larry DoolittleClifford Wolf2015-08-131-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added "scc -expect <N> -nofeedback"Clifford Wolf2015-02-101-7/+48
* namespace YosysClifford Wolf2014-09-271-0/+4
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-061-1/+1
* Using log_assert() instead of assert()Clifford Wolf2014-07-281-3/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-1/+1
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-1/+1
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Moved some passes to other source directoriesClifford Wolf2014-02-081-0/+299