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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-0/+4
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-4/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-3/+3
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-3/+3
* SigSpec refactoring: using the accessor functions everywhereClifford Wolf2014-07-221-1/+1
* SigSpec refactoring: renamed chunks and width to __chunks and __widthClifford Wolf2014-07-221-1/+1
* Some minor documentation fixesClifford Wolf2013-08-211-1/+1
* Added "scatter" commandClifford Wolf2013-06-121-0/+72