iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Use `dict` instead of `std::map`.	Alberto Gonzalez	2020-04-16	1	-9/+9
*	Revert to `stringf()` rather than stringstreams.	Alberto Gonzalez	2020-04-16	1	-12/+8
*	Clean up pseudo-private member usage in `passes/cmds/rename.cc`.	Alberto Gonzalez	2020-04-16	1	-119/+107
*	Add "rename -output"	Clifford Wolf	2019-03-27	1	-3/+23
*	Improve "rename" help message	Clifford Wolf	2019-03-27	1	-0/+6
*	Rename cells based on the wires they drive.	Scott Mansell	2019-01-06	1	-0/+66
*	rename: add -src, for inferring names from source locations.	whitequark	2018-12-05	1	-0/+50
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added design->rename(module, new_name)	Clifford Wolf	2015-06-30	1	-3/+1
*	Added "rename -top new_name"	Clifford Wolf	2015-06-17	1	-0/+27
*	Fixed iterator invalidation bug in "rename" command	Clifford Wolf	2015-02-09	1	-3/+4
*	Added Yosys::{dict,nodict,vector} container types	Clifford Wolf	2014-12-26	1	-4/+4
*	Added missing fixup_ports() calls to "rename" command	Clifford Wolf	2014-11-08	1	-0/+4
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
*	Implemented "rename -enumerate -pattern"	Clifford Wolf	2014-08-26	1	-4/+13
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-7/+7
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-5/+5
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-5/+5
*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-10/+4
*	Added "rename -hide" command	Clifford Wolf	2014-01-02	1	-1/+44
*	Improved handling of private names in opt_clean and rename commands	Clifford Wolf	2013-08-07	1	-5/+37
*	Added renaming of wires and cells to "rename" command	Clifford Wolf	2013-06-19	1	-2/+28
*	Added "rename" command	Clifford Wolf	2013-06-10	1	-0/+94