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* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* Added design->rename(module, new_name)Clifford Wolf2015-06-301-3/+1
* Added "rename -top new_name"Clifford Wolf2015-06-171-0/+27
* Fixed iterator invalidation bug in "rename" commandClifford Wolf2015-02-091-3/+4
* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-261-4/+4
* Added missing fixup_ports() calls to "rename" commandClifford Wolf2014-11-081-0/+4
* namespace YosysClifford Wolf2014-09-271-0/+4
* Implemented "rename -enumerate -pattern"Clifford Wolf2014-08-261-4/+13
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-7/+7
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-5/+5
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-5/+5
* Changed more code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-10/+4
* Added "rename -hide" commandClifford Wolf2014-01-021-1/+44
* Improved handling of private names in opt_clean and rename commandsClifford Wolf2013-08-071-5/+37
* Added renaming of wires and cells to "rename" commandClifford Wolf2013-06-191-2/+28
* Added "rename" commandClifford Wolf2013-06-101-0/+94