Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Added missing fixup_ports() calls to "rename" command | Clifford Wolf | 2014-11-08 | 1 | -0/+4 |
* | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
* | Implemented "rename -enumerate -pattern" | Clifford Wolf | 2014-08-26 | 1 | -4/+13 |
* | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -7/+7 |
* | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
* | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
* | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -10/+4 |
* | Added "rename -hide" command | Clifford Wolf | 2014-01-02 | 1 | -1/+44 |
* | Improved handling of private names in opt_clean and rename commands | Clifford Wolf | 2013-08-07 | 1 | -5/+37 |
* | Added renaming of wires and cells to "rename" command | Clifford Wolf | 2013-06-19 | 1 | -2/+28 |
* | Added "rename" command | Clifford Wolf | 2013-06-10 | 1 | -0/+94 |