| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -3/+3 |
| * | Add "design -import" | Clifford Wolf | 2017-06-30 | 1 | -3/+94 |
| * | Added "design -reset-vlog" | Clifford Wolf | 2016-11-30 | 1 | -7/+32 |
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -2/+2 |
| * | No implicit conversion from IdString to anything else | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Preparations for RTLIL::IdString redesign: cleanup of existing code | Clifford Wolf | 2014-08-02 | 1 | -1/+1 |
| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 1 | -2/+3 |
| * | Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace | Clifford Wolf | 2014-07-31 | 1 | -0/+4 |
| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -11/+11 |
| * | Added "design -push" and "design -pop" | Clifford Wolf | 2014-02-20 | 1 | -8/+45 |
| * | Fixed use of "cmd_error" in passes/cmds/design.cc | Clifford Wolf | 2014-02-07 | 1 | -2/+2 |
| * | Added design -stash/-copy-from/-copy-to | Clifford Wolf | 2014-02-06 | 1 | -13/+99 |
| * | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 | 1 | -0/+128 |
