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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-4/+4
* Warn on empty selection for `add` command.Alberto Gonzalez2020-03-231-0/+4
* Merge pull request #1751 from boqwxp/add_assertN. Engelhardt2020-03-121-1/+57
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| * Extend `add` command to allow adding cells for verification like $assert, $as...Alberto Gonzalez2020-03-101-1/+57
* | Clean up passes/cmds/add.cc code style.Alberto Gonzalez2020-03-101-20/+17
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* Add "add -mod"Clifford Wolf2019-09-201-0/+18
* Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-1/+1
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-2/+2
* Fixed trailing whitespacesClifford Wolf2015-07-021-3/+3
* namespace YosysClifford Wolf2014-09-271-3/+5
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-311-2/+2
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-3/+3
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
* Changed a lot of code to the new RTLIL::Wire constructorsClifford Wolf2014-07-261-4/+1
* Added RTLIL::Cell::has(portname)Clifford Wolf2014-07-261-1/+1
* Manual fixes for new cell connections APIClifford Wolf2014-07-261-1/+1
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-2/+2
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-2/+2
* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-2/+2
* Fixed a bug in "add -global_input"Clifford Wolf2013-11-211-16/+17
* Added "add" command (only wires for now)Clifford Wolf2013-11-201-0/+154