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cmds
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add.cc
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Author
Age
Files
Lines
*
kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
1
-4
/
+4
*
Warn on empty selection for `add` command.
Alberto Gonzalez
2020-03-23
1
-0
/
+4
*
Merge pull request #1751 from boqwxp/add_assert
N. Engelhardt
2020-03-12
1
-1
/
+57
|
\
|
*
Extend `add` command to allow adding cells for verification like $assert, $as...
Alberto Gonzalez
2020-03-10
1
-1
/
+57
*
|
Clean up passes/cmds/add.cc code style.
Alberto Gonzalez
2020-03-10
1
-20
/
+17
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/
*
Add "add -mod"
Clifford Wolf
2019-09-20
1
-0
/
+18
*
Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf
2019-04-18
1
-1
/
+1
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-2
/
+2
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-3
/
+3
*
namespace Yosys
Clifford Wolf
2014-09-27
1
-3
/
+5
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
1
-2
/
+2
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-3
/
+3
*
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf
2014-07-26
1
-4
/
+1
*
Added RTLIL::Cell::has(portname)
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Manual fixes for new cell connections API
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Renamed "placeholder" to "blackbox"
Clifford Wolf
2013-11-22
1
-2
/
+2
*
Fixed a bug in "add -global_input"
Clifford Wolf
2013-11-21
1
-16
/
+17
*
Added "add" command (only wires for now)
Clifford Wolf
2013-11-20
1
-0
/
+154