iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "abc -lut w1:w2"	Clifford Wolf	2015-01-15	1	-5/+21
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*	Fixed typo in ABC command	Clifford Wolf	2014-12-30	1	-2/+2
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*	Less verbose ABC output	Clifford Wolf	2014-12-29	1	-20/+53
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*	Improved ABC clock domain partitioning	Clifford Wolf	2014-12-23	1	-2/+59
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*	Added "abc -markgroups"	Clifford Wolf	2014-12-23	1	-0/+20
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*	Added support for multiple clock domains to "abc" pass	Clifford Wolf	2014-12-21	1	-64/+123
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*	Fixed "abc" pass for clk and enable signals driven by logic	Clifford Wolf	2014-12-21	1	-6/+8
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*	Added DFFE support to "abc" pass	Clifford Wolf	2014-12-20	1	-11/+78
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*	Also look for yosys-abc in parent dir on win32	Clifford Wolf	2014-10-18	1	-0/+5
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*	Header changes so it will compile on VS	William Speirs	2014-10-17	1	-2/+5
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*	More win32/abc fixes	Clifford Wolf	2014-10-12	1	-38/+33
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*	Added make_temp_{file,dir}() and remove_directory() APIs	Clifford Wolf	2014-10-12	1	-31/+15
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*	Using stringf() instead of asprintf() in "abc" pass	Clifford Wolf	2014-10-12	1	-29/+24
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*	Added run_command() api to replace system() and popen()	Clifford Wolf	2014-10-12	1	-73/+70
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*	Added API for generic cell cost calculations	Clifford Wolf	2014-10-09	1	-15/+16
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*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-3/+7
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-0/+4
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*	Small improvements in "abc" command handle_loops() function	Clifford Wolf	2014-09-19	1	-6/+9
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*	Using "NOT" instead of "INV" as cell name in default abc genlib file	Clifford Wolf	2014-09-19	1	-2/+2
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*	Do not run "scorr" in "abc -fast"	Clifford Wolf	2014-09-18	1	-4/+4
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*	Added "abc -fast"	Clifford Wolf	2014-09-18	1	-6/+31
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*	Fixed $_NOR vs. $_NOR_ typo in abc.cc	Clifford Wolf	2014-09-16	1	-1/+1
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*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵	Clifford Wolf	2014-08-16	1	-25/+161
\| \| \| \|	$_OAI4_
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
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*	Added "abc -D" for setting delay target	Clifford Wolf	2014-08-14	1	-5/+18
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*	Filter ANSI escape sequences from ABC output	Clifford Wolf	2014-08-13	1	-0/+15
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-1/+1
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-1/+1
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-32/+32
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-2/+2
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-5/+4
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-2/+2
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-6/+6
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-26/+26
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-6/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-42/+42
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-42/+42
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-32/+10
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-19/+19
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-30/+23
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 1/3	Clifford Wolf	2014-07-23	1	-1/+1
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-34/+34
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-34/+34
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+1
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-2/+7
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Verbose reading of liberty and constr files in ABC pass	Clifford Wolf	2014-03-09	1	-2/+2
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*	Added abc -keepff option	Clifford Wolf	2014-02-14	1	-5/+18
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