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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-0/+4
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-154-6/+6
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
* Replaced sha1 implementationClifford Wolf2014-08-012-9/+3
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-24/+17
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-5/+5
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-272-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-1/+1
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-1/+1
* Fixed manual/CHAPTER_Prog/stubnets.ccClifford Wolf2014-07-231-2/+2
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-12/+7
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-161-3/+4
* small changes in presentationClifford Wolf2014-07-021-5/+2
* Tiny fix in presentationClifford Wolf2014-06-291-1/+1
* Progress in presentationClifford Wolf2014-06-292-0/+97
* Progress in presentationClifford Wolf2014-06-267-79/+105
* Progress in presentationClifford Wolf2014-06-227-42/+503
* fixed typoClifford Wolf2014-06-211-1/+1
* Progress in presentationClifford Wolf2014-06-219-23/+188
* Progress in presentationClifford Wolf2014-06-145-3/+109
* Progress in presentationClifford Wolf2014-05-061-8/+63
* Typos and grammar fixes through chapter 4.Anthony J. Bentley2014-05-022-32/+32
* Typos and grammar fixes through chapter 2.Anthony J. Bentley2014-04-113-21/+21
* POSIX find requires a path argument.Anthony J. Bentley2014-04-041-1/+1
* Progress in presentationClifford Wolf2014-02-216-32/+113
* Progress in presentationClifford Wolf2014-02-215-19/+177
* Progress in presentationClifford Wolf2014-02-204-11/+51
* Progress in presentationClifford Wolf2014-02-205-0/+207
* Progress in presentationClifford Wolf2014-02-2010-10/+152
* Progress in presentationClifford Wolf2014-02-186-3/+72
* Progress in presentationClifford Wolf2014-02-173-9/+37
* Progress in presentationClifford Wolf2014-02-165-1/+80
* Progress in presentationClifford Wolf2014-02-165-1/+79
* Progress in presentationClifford Wolf2014-02-166-3/+74
* Progress in presentationClifford Wolf2014-02-166-1/+114
* Improved "make manual" and "make clean"Clifford Wolf2014-02-113-3/+5
* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+4
* presentation progressClifford Wolf2014-02-0610-12/+265
* presentation progressClifford Wolf2014-02-054-64/+221
* presentation progressClifford Wolf2014-02-055-3/+62
* presentation progressClifford Wolf2014-02-055-8/+230
* presentation progressClifford Wolf2014-02-043-34/+104
* presentation progressClifford Wolf2014-02-049-3/+206
* presentation progressClifford Wolf2014-02-042-11/+55
* presentation progressClifford Wolf2014-02-036-1/+152
* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+7
* presentation progressClifford Wolf2014-02-0219-40/+194