| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Some fixes in presentation | Clifford Wolf | 2014-11-08 | 2 | -2/+2 | |
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| | * | Various documentation updates | Clifford Wolf | 2014-11-08 | 12 | -108/+1276 | |
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| | * | Renamed SIZE() to GetSize() because of name collision on Win32 | Clifford Wolf | 2014-10-10 | 2 | -3/+3 | |
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| * | | appnote for verilog to btor | Ahmed Irfan | 2015-04-03 | 1 | -0/+435 | |
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| * | Added $lcu cell type | Clifford Wolf | 2014-09-08 | 1 | -1/+1 | |
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| * | Corrected spelling mistakes found by lintian | Ruben Undheim | 2014-09-06 | 5 | -13/+13 | |
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| * | Removed $bu0 cell type | Clifford Wolf | 2014-09-04 | 3 | -8/+2 | |
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| * | Removed references to yosys-svgviewer from docs | Clifford Wolf | 2014-09-02 | 2 | -21/+10 | |
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| * | Added $alu cell type | Clifford Wolf | 2014-08-30 | 1 | -0/+4 | |
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| * | Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵ | Clifford Wolf | 2014-08-16 | 1 | -0/+4 | |
| | | | | | $_OAI4_ | |||||
| * | Renamed $_INV_ cell type to $_NOT_ | Clifford Wolf | 2014-08-15 | 4 | -6/+6 | |
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| * | Removed old doc references to $safe_pmux | Clifford Wolf | 2014-08-15 | 2 | -5/+1 | |
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| * | RIP $safe_pmux | Clifford Wolf | 2014-08-14 | 1 | -1/+1 | |
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| * | Replaced sha1 implementation | Clifford Wolf | 2014-08-01 | 2 | -9/+3 | |
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| * | Added module->design and cell->module, wire->module pointers | Clifford Wolf | 2014-07-31 | 2 | -24/+17 | |
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| * | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 1 | -1/+1 | |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 2 | -5/+5 | |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 2 | -2/+2 | |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 2 | -4/+4 | |
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| * | Changed users of cell->connections_ to the new API (sed command) | Clifford Wolf | 2014-07-26 | 1 | -1/+1 | |
| | | | | | | | | | | git grep -l 'connections_' | xargs sed -i -r -e ' s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g; s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g; s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g; s/(->|\.)connections_.push_back/\1connect/g; s/(->|\.)connections_/\1connections()/g;' | |||||
| * | Renamed RTLIL::{Module,Cell}::connections to connections_ | Clifford Wolf | 2014-07-26 | 1 | -1/+1 | |
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| * | Fixed manual/CHAPTER_Prog/stubnets.cc | Clifford Wolf | 2014-07-23 | 1 | -2/+2 | |
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| * | Removed RTLIL::SigSpec::expand() method | Clifford Wolf | 2014-07-23 | 1 | -12/+7 | |
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| * | Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal | Clifford Wolf | 2014-07-16 | 1 | -3/+4 | |
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| * | small changes in presentation | Clifford Wolf | 2014-07-02 | 1 | -5/+2 | |
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| * | Tiny fix in presentation | Clifford Wolf | 2014-06-29 | 1 | -1/+1 | |
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| * | Progress in presentation | Clifford Wolf | 2014-06-29 | 2 | -0/+97 | |
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| * | Progress in presentation | Clifford Wolf | 2014-06-26 | 7 | -79/+105 | |
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| * | Progress in presentation | Clifford Wolf | 2014-06-22 | 7 | -42/+503 | |
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| * | fixed typo | Clifford Wolf | 2014-06-21 | 1 | -1/+1 | |
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| * | Progress in presentation | Clifford Wolf | 2014-06-21 | 9 | -23/+188 | |
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| * | Progress in presentation | Clifford Wolf | 2014-06-14 | 5 | -3/+109 | |
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| * | Progress in presentation | Clifford Wolf | 2014-05-06 | 1 | -8/+63 | |
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| * | Typos and grammar fixes through chapter 4. | Anthony J. Bentley | 2014-05-02 | 2 | -32/+32 | |
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| * | Typos and grammar fixes through chapter 2. | Anthony J. Bentley | 2014-04-11 | 3 | -21/+21 | |
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| * | POSIX find requires a path argument. | Anthony J. Bentley | 2014-04-04 | 1 | -1/+1 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-21 | 6 | -32/+113 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-21 | 5 | -19/+177 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-20 | 4 | -11/+51 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-20 | 5 | -0/+207 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-20 | 10 | -10/+152 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-18 | 6 | -3/+72 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-17 | 3 | -9/+37 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-16 | 5 | -1/+80 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-16 | 5 | -1/+79 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-16 | 6 | -3/+74 | |
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| * | Progress in presentation | Clifford Wolf | 2014-02-16 | 6 | -1/+114 | |
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| * | Improved "make manual" and "make clean" | Clifford Wolf | 2014-02-11 | 3 | -3/+5 | |
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| * | Added $slice and $concat cell types | Clifford Wolf | 2014-02-07 | 1 | -0/+4 | |
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| * | presentation progress | Clifford Wolf | 2014-02-06 | 10 | -12/+265 | |
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