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| * Added $assume cell typeClifford Wolf2015-02-261-1/+1
| * Fixed creation of command reference in manualClifford Wolf2015-02-091-5/+5
| * Updated command reference in manualClifford Wolf2015-02-091-75/+440
| * Various presentation fixesClifford Wolf2015-02-092-8/+15
| * Added $equiv cell typeClifford Wolf2015-01-191-1/+1
| * Improvements in CodingReadmeClifford Wolf2014-12-311-8/+13
| * Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-081-1/+9
| * manual/presentation.tex: bg option is unknown with beamer 3.3 in beamercolorboxFabien Marteau2014-12-071-1/+1
| * suppressing semi-colon at the end of dot filesFabien Marteau2014-12-0519-19/+19
| * Added some missing .gitignore in manual/Clifford Wolf2014-12-042-0/+4
| * Some fixes in stubnets exampleClifford Wolf2014-11-241-3/+5
| * Some fixes in presentationClifford Wolf2014-11-082-2/+2
| * Various documentation updatesClifford Wolf2014-11-0812-108/+1276
| * Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-102-3/+3
* | appnote for verilog to btorAhmed Irfan2015-04-031-0/+435
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* Added $lcu cell typeClifford Wolf2014-09-081-1/+1
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-065-13/+13
* Removed $bu0 cell typeClifford Wolf2014-09-043-8/+2
* Removed references to yosys-svgviewer from docsClifford Wolf2014-09-022-21/+10
* Added $alu cell typeClifford Wolf2014-08-301-0/+4
* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...Clifford Wolf2014-08-161-0/+4
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-154-6/+6
* Removed old doc references to $safe_pmuxClifford Wolf2014-08-152-5/+1
* RIP $safe_pmuxClifford Wolf2014-08-141-1/+1
* Replaced sha1 implementationClifford Wolf2014-08-012-9/+3
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-24/+17
* Renamed "stdcells.v" to "techmap.v"Clifford Wolf2014-07-311-1/+1
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-272-5/+5
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-272-2/+2
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-272-4/+4
* Changed users of cell->connections_ to the new API (sed command)Clifford Wolf2014-07-261-1/+1
* Renamed RTLIL::{Module,Cell}::connections to connections_Clifford Wolf2014-07-261-1/+1
* Fixed manual/CHAPTER_Prog/stubnets.ccClifford Wolf2014-07-231-2/+2
* Removed RTLIL::SigSpec::expand() methodClifford Wolf2014-07-231-12/+7
* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-161-3/+4
* small changes in presentationClifford Wolf2014-07-021-5/+2
* Tiny fix in presentationClifford Wolf2014-06-291-1/+1
* Progress in presentationClifford Wolf2014-06-292-0/+97
* Progress in presentationClifford Wolf2014-06-267-79/+105
* Progress in presentationClifford Wolf2014-06-227-42/+503
* fixed typoClifford Wolf2014-06-211-1/+1
* Progress in presentationClifford Wolf2014-06-219-23/+188
* Progress in presentationClifford Wolf2014-06-145-3/+109
* Progress in presentationClifford Wolf2014-05-061-8/+63
* Typos and grammar fixes through chapter 4.Anthony J. Bentley2014-05-022-32/+32
* Typos and grammar fixes through chapter 2.Anthony J. Bentley2014-04-113-21/+21
* POSIX find requires a path argument.Anthony J. Bentley2014-04-041-1/+1
* Progress in presentationClifford Wolf2014-02-216-32/+113
* Progress in presentationClifford Wolf2014-02-215-19/+177
* Progress in presentationClifford Wolf2014-02-204-11/+51