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* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-3/+3
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Added some missing .gitignore in manual/Clifford Wolf2014-12-041-0/+1
* Various documentation updatesClifford Wolf2014-11-081-1/+6
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-101-1/+1
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-24/+17
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-271-4/+4
* Refactoring: Renamed RTLIL::Module::cells to cells_Clifford Wolf2014-07-271-1/+1
* Refactoring: Renamed RTLIL::Module::wires to wires_Clifford Wolf2014-07-271-3/+3
* Progress in presentationClifford Wolf2014-06-225-0/+103