index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
manual
/
CHAPTER_Prog
/
stubnets.cc
Commit message (
Expand
)
Author
Age
Files
Lines
*
Consistent use of 'override' for virtual methods in derived classes.
Henner Zeller
2018-07-20
1
-1
/
+1
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
1
-1
/
+1
*
Spell check (by Larry Doolittle)
Clifford Wolf
2015-08-14
1
-1
/
+1
*
Fixed trailing whitespaces
Clifford Wolf
2015-07-02
1
-1
/
+1
*
Some fixes in stubnets example
Clifford Wolf
2014-11-24
1
-3
/
+5
*
Renamed SIZE() to GetSize() because of name collision on Win32
Clifford Wolf
2014-10-10
1
-2
/
+2
*
Corrected spelling mistakes found by lintian
Ruben Undheim
2014-09-06
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf
2014-07-27
1
-1
/
+1
*
Changed users of cell->connections_ to the new API (sed command)
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Renamed RTLIL::{Module,Cell}::connections to connections_
Clifford Wolf
2014-07-26
1
-1
/
+1
*
Fixed manual/CHAPTER_Prog/stubnets.cc
Clifford Wolf
2014-07-23
1
-2
/
+2
*
Removed RTLIL::SigSpec::expand() method
Clifford Wolf
2014-07-23
1
-12
/
+7
*
Renamed manual/FILES_* directories
Clifford Wolf
2014-01-28
1
-0
/
+133