index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
manual
/
CHAPTER_CellLib.tex
Commit message (
Expand
)
Author
Age
Files
Lines
*
Added more documentation fixmes for nontrivial register cells
Clifford Wolf
2014-12-08
1
-1
/
+9
*
Added $lcu cell type
Clifford Wolf
2014-09-08
1
-1
/
+1
*
Removed $bu0 cell type
Clifford Wolf
2014-09-04
1
-6
/
+0
*
Added $alu cell type
Clifford Wolf
2014-08-30
1
-0
/
+4
*
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...
Clifford Wolf
2014-08-16
1
-0
/
+4
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
1
-2
/
+2
*
Removed old doc references to $safe_pmux
Clifford Wolf
2014-08-15
1
-4
/
+0
*
Changed the $mem/$memwr WR_EN input to a per-data-bit enable signal
Clifford Wolf
2014-07-16
1
-3
/
+4
*
Added $slice and $concat cell types
Clifford Wolf
2014-02-07
1
-0
/
+4
*
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Clifford Wolf
2014-02-03
1
-0
/
+7
*
Added $assert cell
Clifford Wolf
2014-01-19
1
-0
/
+4
*
Added correct handling of $memwr priority
Clifford Wolf
2014-01-03
1
-0
/
+3
*
Added new cell types to manual
Clifford Wolf
2013-12-28
1
-0
/
+9
*
Moved common techlib files to techlibs/common
Clifford Wolf
2013-09-15
1
-2
/
+2
*
Added Yosys Manual
Clifford Wolf
2013-07-20
1
-0
/
+408