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path: root/manual/CHAPTER_CellLib.tex
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* Added read-enable to memory modelClifford Wolf2015-09-251-2/+6
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
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* Added $assume cell typeClifford Wolf2015-02-261-1/+1
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* Added $equiv cell typeClifford Wolf2015-01-191-1/+1
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* Added more documentation fixmes for nontrivial register cellsClifford Wolf2014-12-081-1/+9
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* Added $lcu cell typeClifford Wolf2014-09-081-1/+1
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* Removed $bu0 cell typeClifford Wolf2014-09-041-6/+0
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* Added $alu cell typeClifford Wolf2014-08-301-0/+4
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* Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ ↵Clifford Wolf2014-08-161-0/+4
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-151-2/+2
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* Removed old doc references to $safe_pmuxClifford Wolf2014-08-151-4/+0
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* Changed the $mem/$memwr WR_EN input to a per-data-bit enable signalClifford Wolf2014-07-161-3/+4
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* Added $slice and $concat cell typesClifford Wolf2014-02-071-0/+4
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* Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)Clifford Wolf2014-02-031-0/+7
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* Added $assert cellClifford Wolf2014-01-191-0/+4
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* Added correct handling of $memwr priorityClifford Wolf2014-01-031-0/+3
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* Added new cell types to manualClifford Wolf2013-12-281-0/+9
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-151-2/+2
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* Added Yosys ManualClifford Wolf2013-07-201-0/+408