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Author
Age
Files
Lines
*
Improvements in assertpmux
Clifford Wolf
2016-09-07
2
-0
/
+19
*
Removed $aconst cell type
Clifford Wolf
2016-08-30
2
-2
/
+1
*
Removed $predict again
Clifford Wolf
2016-08-28
3
-11
/
+1
*
Fixed handling of transparent bram rd ports on ROMs
Clifford Wolf
2016-08-27
1
-0
/
+1
*
Added glob support to all front-ends
Clifford Wolf
2016-08-22
3
-4
/
+38
*
Add MSYS2-compatible build.
William D. Jones
2016-08-16
1
-2
/
+1
*
Use _Exit(0) on win32, always use _Exit(1) in log_error()
Clifford Wolf
2016-08-16
2
-1
/
+6
*
Added log_const() API
Clifford Wolf
2016-08-09
2
-0
/
+19
*
Use /proc/self/exe on Cygwin as well.
Yury Gribov
2016-08-08
1
-1
/
+1
*
Added SatGen support for $anyconst
Clifford Wolf
2016-07-27
1
-0
/
+22
*
Removed $predict support from SatGen
Clifford Wolf
2016-07-27
1
-9
/
+0
*
Added $anyconst and $aconst
Clifford Wolf
2016-07-27
2
-0
/
+8
*
Added "read_verilog -dump_rtlil"
Clifford Wolf
2016-07-27
2
-0
/
+8
*
Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell()
Clifford Wolf
2016-07-25
2
-2
/
+2
*
Improvements in CellEdgesDatabase
Clifford Wolf
2016-07-24
2
-13
/
+134
*
Added CellEdgesDatabase API
Clifford Wolf
2016-07-24
2
-0
/
+151
*
Added satgen initstate support
Clifford Wolf
2016-07-22
1
-0
/
+27
*
Added $initstate cell type and vlog function
Clifford Wolf
2016-07-21
3
-3
/
+10
*
After reading the SV spec, using non-standard predict() instead of expect()
Clifford Wolf
2016-07-21
3
-4
/
+4
*
Added basic support for $expect cells
Clifford Wolf
2016-07-13
4
-8
/
+29
*
A few modifications after pull request comments
Ruben Undheim
2016-06-18
2
-3
/
+2
*
Added support for SystemVerilog packages with localparam definitions
Ruben Undheim
2016-06-18
2
-0
/
+4
*
Added $sop SAT model
Clifford Wolf
2016-06-17
1
-0
/
+82
*
Improved support for $sop cells
Clifford Wolf
2016-06-17
2
-4
/
+16
*
Added $sop cell type and "abc -sop"
Clifford Wolf
2016-06-17
2
-1
/
+36
*
Added missing "#define HASHLIB_H"
Clifford Wolf
2016-05-14
1
-0
/
+1
*
Include <cmath> in yosys.h
Clifford Wolf
2016-05-08
1
-0
/
+1
*
Fixes for MXE build
Clifford Wolf
2016-05-07
2
-8
/
+8
*
Added "yosys -D ALL"
Clifford Wolf
2016-04-24
3
-6
/
+22
*
Added "yosys -D" feature
Clifford Wolf
2016-04-21
4
-9
/
+36
*
Minor hashlib bugfix
Clifford Wolf
2016-04-16
1
-1
/
+1
*
Hashlib indenting fix
Clifford Wolf
2016-04-05
1
-2
/
+2
*
Added ScriptPass helper class for script-like passes
Clifford Wolf
2016-03-31
3
-3
/
+79
*
Added log_dump() support for dict<> and pool<> containers
Clifford Wolf
2016-03-31
1
-0
/
+26
*
We have 2016 for a while now
Clifford Wolf
2016-03-30
1
-1
/
+1
*
Added .vhd file extension support
Clifford Wolf
2016-03-30
1
-0
/
+2
*
Merge pull request #137 from ravenexp/master
Clifford Wolf
2016-03-28
1
-0
/
+5
|
\
|
*
Embed DATDIR make variable value into yosys binary.
Sergey Kvachonok
2016-03-26
1
-0
/
+5
*
|
fix a cut-n-paste error in the -h help
Sebastian Kuzminsky
2016-03-26
1
-2
/
+2
|
/
*
Use easyer-to-read unoptimized ceil_log2()
Clifford Wolf
2016-02-15
1
-18
/
+5
*
Fixed more visual studio warnings
Clifford Wolf
2016-02-14
1
-5
/
+3
*
Fixed some visual studio warnings
Clifford Wolf
2016-02-13
3
-4
/
+4
*
Added "int ceil_log2(int)" function
Clifford Wolf
2016-02-13
2
-0
/
+26
*
Added addBufGate module method
Clifford Wolf
2016-02-02
2
-0
/
+3
*
SigMap performance improvement
Clifford Wolf
2016-02-01
1
-1
/
+7
*
hashlib mfp<> performance improvements
Clifford Wolf
2016-02-01
1
-2
/
+7
*
Added reserve() method to haslib classes and
Clifford Wolf
2016-01-31
1
-2
/
+6
*
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
Rick Altherr
2016-01-31
1
-2
/
+31
*
rtlil: speed up SigSpec::sort_and_unify()
Rick Altherr
2016-01-31
1
-1
/
+11
*
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
Rick Altherr
2016-01-31
1
-6
/
+14
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