iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12	1	-1/+1
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*	Another build fix by americanrouter (via reddit)	Clifford Wolf	2014-08-11	1	-0/+3
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*	Fixed build with gcc-4.6	Clifford Wolf	2014-08-07	3	-3/+11
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*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	3	-8/+53
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*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-5/+18
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*	Added query() API to ModIndex	Clifford Wolf	2014-08-03	1	-8/+46
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*	Added ID() macro for static IdStrings	Clifford Wolf	2014-08-03	1	-0/+3
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*	Fixed a va_list corruption in logv_error()	Clifford Wolf	2014-08-02	1	-4/+3
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*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-10/+16
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*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	2	-7/+6
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*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	4	-22/+22
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*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	3	-17/+31
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*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02	2	-2/+9
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*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	5	-33/+65
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*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	2	-15/+90
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*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	2	-63/+36
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*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	6	-22/+61
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*	Added logfile hash to statistics footer	Clifford Wolf	2014-08-01	5	-45/+79
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*	Added per-pass cpu usage statistics	Clifford Wolf	2014-08-01	4	-12/+86
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*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	7	-24/+165
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*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	2	-10/+14
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*	Renamed modwalker.h to modtools.h	Clifford Wolf	2014-07-31	1	-2/+2
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	4	-179/+206
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*	Added "trace" command	Clifford Wolf	2014-07-31	1	-0/+3
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*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	2	-96/+97
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*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	2	-0/+103
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*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	11	-597/+653
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*	Added "yosys -A"	Clifford Wolf	2014-07-31	1	-1/+10
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*	Added "yosys -Q"	Clifford Wolf	2014-07-31	1	-26/+35
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*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-0/+3
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*	Added write_file command	Clifford Wolf	2014-07-30	2	-5/+7
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*	Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models	Clifford Wolf	2014-07-30	1	-36/+39
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*	Added "log_dump_val_worker(char *v)"	Clifford Wolf	2014-07-30	1	-0/+1
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*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30	7	-60/+132
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*	Added "test_cell" command	Clifford Wolf	2014-07-29	1	-1/+1
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	1	-1/+3
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*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	2	-0/+10
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*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	5	-19/+75
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*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	2	-1/+3
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	12	-144/+157
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*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	2	-0/+15
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*	Added cover() to all SigSpec constructors	Clifford Wolf	2014-07-28	1	-0/+22
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*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	2	-4/+42
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-1/+2
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*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-0/+5
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*	Small improvements in PerformanceTimer API	Clifford Wolf	2014-07-27	1	-6/+7
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*	Improved performance of opt_const on large modules	Clifford Wolf	2014-07-27	1	-0/+103
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*	Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs	Clifford Wolf	2014-07-27	1	-9/+26
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*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
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