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| | * | The share directory cannot be searched when used as a Python library, only in...Benedikt Tutzer2018-08-202-1/+8
| | * | Python passes are now looked for in share/plugins and can be added by specify...Benedikt Tutzer2018-08-201-4/+1
| | * | Fixed issue when using a python plugin in the yosys shellBenedikt Tutzer2018-08-203-4/+28
| | * | Python Passes can now be added with the -m option or with the plugin command....Benedikt Tutzer2018-08-163-1/+96
| | * | Added Wrappers for:Benedikt Tutzer2018-08-133-142/+2923
| | * | Saving id and pointer to c++ object. Object is valid only if both id and poin...Benedikt Tutzer2018-08-011-8/+29
| | * | Setup is called automatically when the module is loaded, shutdown when python...Benedikt Tutzer2018-08-011-16/+19
| | * | Cleaned up commentsBenedikt Tutzer2018-08-011-9/+3
| | * | Added Monitor class that can monitor all changes in a Design or in a ModuleBenedikt Tutzer2018-07-101-0/+119
| | * | added destructors for wires and cellsBenedikt Tutzer2018-07-102-1/+16
| | * | removed debug outputBenedikt Tutzer2018-07-091-1/+0
| | * | commands can now be run on arbitrary designs, not only on the active oneBenedikt Tutzer2018-07-091-0/+10
| | * | multiple designs can now exist independent from each other. Cells/Wires/Modul...Benedikt Tutzer2018-07-093-45/+118
| | * | Introduced namespace and removed class-prefixes to increase readabilityBenedikt Tutzer2018-06-281-163/+165
| | * | changed references from hash-ids to IdString namesBenedikt Tutzer2018-06-281-64/+32
| | * | added wrappers for Design, Modules, Cells and WiresBenedikt Tutzer2018-06-251-0/+244
* | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-202-3/+6
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| * | | Add "wbflip" commandClifford Wolf2019-04-202-3/+6
| * | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
* | | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
* | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaigEddie Hung2019-04-182-3/+7
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| * | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-182-3/+7
* | | | Merge branch 'master' into xaigEddie Hung2019-04-087-27/+151
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| * | | Add "read_ilang -lib"Clifford Wolf2019-04-052-0/+25
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| * | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-232-1/+9
| * | Add fmcombine passClifford Wolf2019-03-152-17/+32
| * | Add hashlib "<container>::element(int n)" methodsClifford Wolf2019-03-141-0/+6
| * | Fix a bug in handling quotes in multi-cmd lines in Yosys scriptsClifford Wolf2019-03-121-1/+7
| * | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-114-5/+67
| * | Add ENABLE_GLOB Makefile switchClifford Wolf2019-03-111-3/+5
* | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-261-2/+16
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| * | Merge pull request #819 from YosysHQ/clifford/optdClifford Wolf2019-02-221-2/+16
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| | * | Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"Clifford Wolf2019-02-211-3/+3
| | * | Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behaviorClifford Wolf2019-02-211-2/+16
* | | | Add IdString::ends_with()Eddie Hung2019-02-261-0/+6
* | | | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-02-211-0/+3
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| * | | Add FF support to wreduceClifford Wolf2019-02-201-0/+3
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* / / Refactor kernel/cost.h definition into cost.ccEddie Hung2019-02-082-49/+77
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* | Add optional nullstr argument to log_id()Clifford Wolf2019-01-151-1/+3
* | Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-022-2/+2
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-232-0/+14
* | tcl: add support for passing arguments to scripts.whitequark2018-12-201-7/+18
* | Improve ConstEval error handling for non-eval cell typesClifford Wolf2018-11-292-9/+19
* | Avoid assert when label is an empty stringJon Burgess2018-10-281-1/+1
* | fix unhandled std::out_of_range when calling yosys with 3-character argumentwhentze2018-10-221-2/+2
* | Documentation improvements etc.Ruben Undheim2018-10-131-3/+1
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-122-2/+2
* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-122-0/+17
* | Fix IdString M in setup_stdcells()Adrian Wheeldon2018-10-041-1/+1
* | Fix Cygwin build and document needed packagesMiodrag Milanovic2018-09-191-1/+1
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