index
:
iCE40/yosys
master
[no description]
about
summary
refs
log
tree
commit
diff
stats
log msg
author
committer
range
path:
root
/
kernel
Commit message (
Expand
)
Author
Age
Files
Lines
...
|
|
*
|
The share directory cannot be searched when used as a Python library, only in...
Benedikt Tutzer
2018-08-20
2
-1
/
+8
|
|
*
|
Python passes are now looked for in share/plugins and can be added by specify...
Benedikt Tutzer
2018-08-20
1
-4
/
+1
|
|
*
|
Fixed issue when using a python plugin in the yosys shell
Benedikt Tutzer
2018-08-20
3
-4
/
+28
|
|
*
|
Python Passes can now be added with the -m option or with the plugin command....
Benedikt Tutzer
2018-08-16
3
-1
/
+96
|
|
*
|
Added Wrappers for:
Benedikt Tutzer
2018-08-13
3
-142
/
+2923
|
|
*
|
Saving id and pointer to c++ object. Object is valid only if both id and poin...
Benedikt Tutzer
2018-08-01
1
-8
/
+29
|
|
*
|
Setup is called automatically when the module is loaded, shutdown when python...
Benedikt Tutzer
2018-08-01
1
-16
/
+19
|
|
*
|
Cleaned up comments
Benedikt Tutzer
2018-08-01
1
-9
/
+3
|
|
*
|
Added Monitor class that can monitor all changes in a Design or in a Module
Benedikt Tutzer
2018-07-10
1
-0
/
+119
|
|
*
|
added destructors for wires and cells
Benedikt Tutzer
2018-07-10
2
-1
/
+16
|
|
*
|
removed debug output
Benedikt Tutzer
2018-07-09
1
-1
/
+0
|
|
*
|
commands can now be run on arbitrary designs, not only on the active one
Benedikt Tutzer
2018-07-09
1
-0
/
+10
|
|
*
|
multiple designs can now exist independent from each other. Cells/Wires/Modul...
Benedikt Tutzer
2018-07-09
3
-45
/
+118
|
|
*
|
Introduced namespace and removed class-prefixes to increase readability
Benedikt Tutzer
2018-06-28
1
-163
/
+165
|
|
*
|
changed references from hash-ids to IdString names
Benedikt Tutzer
2018-06-28
1
-64
/
+32
|
|
*
|
added wrappers for Design, Modules, Cells and Wires
Benedikt Tutzer
2018-06-25
1
-0
/
+244
*
|
|
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-04-20
2
-3
/
+6
|
\
|
|
|
|
*
|
|
Add "wbflip" command
Clifford Wolf
2019-04-20
2
-3
/
+6
|
*
|
|
Ignore 'whitebox' attr in flatten with "-wb" option
Eddie Hung
2019-04-18
1
-2
/
+2
*
|
|
|
Ignore 'whitebox' attr in flatten with "-wb" option
Eddie Hung
2019-04-18
1
-2
/
+2
*
|
|
|
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
Eddie Hung
2019-04-18
2
-3
/
+7
|
\
|
|
|
|
*
|
|
Add "whitebox" attribute, add "read_verilog -wb"
Clifford Wolf
2019-04-18
2
-3
/
+7
*
|
|
|
Merge branch 'master' into xaig
Eddie Hung
2019-04-08
7
-27
/
+151
|
\
|
|
|
|
*
|
|
Add "read_ilang -lib"
Clifford Wolf
2019-04-05
2
-0
/
+25
|
|
|
/
|
|
/
|
|
*
|
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Clifford Wolf
2019-03-23
2
-1
/
+9
|
*
|
Add fmcombine pass
Clifford Wolf
2019-03-15
2
-17
/
+32
|
*
|
Add hashlib "<container>::element(int n)" methods
Clifford Wolf
2019-03-14
1
-0
/
+6
|
*
|
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
Clifford Wolf
2019-03-12
1
-1
/
+7
|
*
|
Improve determinism of IdString DB for similar scripts
Clifford Wolf
2019-03-11
4
-5
/
+67
|
*
|
Add ENABLE_GLOB Makefile switch
Clifford Wolf
2019-03-11
1
-3
/
+5
*
|
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-02-26
1
-2
/
+16
|
\
|
|
|
*
|
Merge pull request #819 from YosysHQ/clifford/optd
Clifford Wolf
2019-02-22
1
-2
/
+16
|
|
\
\
|
|
*
|
Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"
Clifford Wolf
2019-02-21
1
-3
/
+3
|
|
*
|
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
Clifford Wolf
2019-02-21
1
-2
/
+16
*
|
|
|
Add IdString::ends_with()
Eddie Hung
2019-02-26
1
-0
/
+6
*
|
|
|
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-02-21
1
-0
/
+3
|
\
|
|
|
|
*
|
|
Add FF support to wreduce
Clifford Wolf
2019-02-20
1
-0
/
+3
|
|
/
/
*
/
/
Refactor kernel/cost.h definition into cost.cc
Eddie Hung
2019-02-08
2
-49
/
+77
|
/
/
*
|
Add optional nullstr argument to log_id()
Clifford Wolf
2019-01-15
1
-1
/
+3
*
|
Fix typographical and grammatical errors and inconsistencies.
whitequark
2019-01-02
2
-2
/
+2
*
|
proc_clean: remove any empty cases if all cases use all-def compare.
whitequark
2018-12-23
2
-0
/
+14
*
|
tcl: add support for passing arguments to scripts.
whitequark
2018-12-20
1
-7
/
+18
*
|
Improve ConstEval error handling for non-eval cell types
Clifford Wolf
2018-11-29
2
-9
/
+19
*
|
Avoid assert when label is an empty string
Jon Burgess
2018-10-28
1
-1
/
+1
*
|
fix unhandled std::out_of_range when calling yosys with 3-character argument
whentze
2018-10-22
1
-2
/
+2
*
|
Documentation improvements etc.
Ruben Undheim
2018-10-13
1
-3
/
+1
*
|
Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
2
-2
/
+2
*
|
Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
2
-0
/
+17
*
|
Fix IdString M in setup_stdcells()
Adrian Wheeldon
2018-10-04
1
-1
/
+1
*
|
Fix Cygwin build and document needed packages
Miodrag Milanovic
2018-09-19
1
-1
/
+1
[prev]
[next]