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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-263-10/+10
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-1/+5
| | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* Respect \A_SIGNED for $shiftXiretza2020-08-182-42/+22
| | | | | | This reflects the behaviour of $shr/$shl, which sign-extend their A operands to the size of their output, then do a logical shift (shift in 0-bits).
* async2sync: Support all FF types.Marcelina Kościelnicka2020-07-301-0/+46
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* ffinit: Fortify the code a bit.Marcelina Kościelnicka2020-07-281-24/+19
| | | | | This fixes handling of messy cases involving repeatedly setting and removing the same init bit.
* satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-242-4/+67
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* Add utility module for representing flip-flops.Marcelina Kościelnicka2020-07-231-0/+440
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* Add utility module for dealing with init attributes.Marcelina Kościelnicka2020-07-231-0/+146
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+1
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* celltypes: Fix EN port name for some FF types.Marcelina Kościelnicka2020-07-201-4/+4
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* satgen: Move importCell out of the header.Marcelina Kościelnicka2020-07-192-1165/+1189
| | | | | This function has no hope of ever getting inlined anyway, and it speeds up yosys compile time by 7%.
* verilog_backend: add `-sv` option, make `-o <filename>.sv` work.whitequark2020-07-161-0/+2
| | | | See #2271.
* Merge pull request #2168 from whitequark/assert-unused-exprsclairexen2020-06-254-9/+14
|\ | | | | Use (and ignore) the expression provided to log_assert in NDEBUG builds
| * Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).whitequark2020-06-191-0/+8
| | | | | | | | | | [[maybe_unused]] is available since C++17, so this commit adds a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
| * Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().whitequark2020-06-192-4/+4
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| * Use (and ignore) the expression provided to log_debug in NDEBUG builds.whitequark2020-06-191-2/+1
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| * Use (and ignore) the expression provided to log_assert in NDEBUG builds.whitequark2020-06-192-3/+1
| | | | | | | | | | This avoids warnings in NDEBUG builds emitted when a variable is only used in log_assert, but is always defined.
* | Merge pull request #2135 from boqwxp/qbfsat-timeinfoclairexen2020-06-251-10/+8
|\ \ | | | | | | log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
| * | log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`.Alberto Gonzalez2020-06-211-4/+0
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| * | log, qbfsat: Include child process time in `PerformanceTimer::query()` and ↵Alberto Gonzalez2020-06-211-6/+8
| | | | | | | | | | | | report the time for each call to the QBF-SAT solver.
| * | qbfsat: Simplify solution format and replace `SigBit::str()` with ↵Alberto Gonzalez2020-06-211-8/+0
| | | | | | | | | | | | | | | | | | `log_signal()`. Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
| * | qbfsat: Use bit precise mapping for hole value wires and a more robust hole ↵Alberto Gonzalez2020-06-211-0/+8
| | | | | | | | | | | | spec for writing to and specializing from a solution file.
* | | Add add* functions for the new FF typesMarcelina Kościelnicka2020-06-232-0/+213
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* | | Add new builtin FF typesMarcelina Kościelnicka2020-06-233-47/+267
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | The new types include: - FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`) - FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`) - FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`) - FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`) - FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`) - latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`) The new FF types are not actually used anywhere yet (this is left for future commits).
* | Merge pull request #2177 from boqwxp/dict-iterator-jumpwhitequark2020-06-212-0/+25
|\ \ | | | | | | hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
| * | dict: Remove guard for past-the-end iterators that might mask problems in ↵Alberto Gonzalez2020-06-191-2/+2
| | | | | | | | | | | | | | | | | | static analysis. Co-Authored-By: whitequark <whitequark@whitequark.org>
| * | hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and ↵Alberto Gonzalez2020-06-192-0/+25
| |/ | | | | | | `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
* / rtlil: Add `Design::select()` for selecting whole modules.Alberto Gonzalez2020-06-191-0/+7
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* Add missing [[noreturn]] to log_file_error()Xiretza2020-06-191-1/+1
| | | | | | | | | | | | | Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not YS_NORETURN, so it got lost in #2173, resulting in warnings in frontends/ast/simplify.cc: frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^ frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn] } ^
* Use C++11 [[noreturn]] attribute.whitequark2020-06-193-8/+5
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* Use C++11 final/override keywords.whitequark2020-06-186-33/+25
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* MSVC defines TRANSPARENT tooAnonymous Maarten2020-06-171-4/+4
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* kernel: guard include of signal.h more precisely.whitequark2020-06-131-1/+3
| | | | | | Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM does not have signals. (Arguably Yosys was broken even before, it was just broken silently.)
* RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.whitequark2020-06-092-2/+12
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* flatten: preserve original object names via hdlname attribute.whitequark2020-06-082-0/+19
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* RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.whitequark2020-06-081-2/+2
| | | | | The only difference in behavior is that this removes the attribute when the pool becomes empty.
* Merge pull request #2085 from rswarbrick/selectclairexen2020-06-081-1/+1
|\ | | | | Silence warning in select.cc and pass some more args by ref
| * Pass some more args by reference in select.ccRupert Swarbrick2020-05-271-1/+1
| | | | | | | | | | | | | | | | | | Before this patch, the code passed around std::string objects by value. It's probably not a hot-spot, but it can't hurt to avoid the copying. Removing the copy and clean-up code means the resulting code is ~6.1kb smaller when compiled with GCC 9.3 and standard settings.
* | Merge pull request #2105 from whitequark/split-flatten-off-techmapclairexen2020-06-082-0/+14
|\ \ | | | | | | Split `flatten` from `techmap` and simplify it
| * | RTLIL: factor out RTLIL::Module::addMemory. NFC.whitequark2020-06-042-0/+14
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* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-042-1/+3
|\ \ \ | | | | | | | | Preserve 'signed'-ness of a verilog wire through RTLIL
| * | | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-272-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now: RTLIL::wire holds an is_signed field. This is exported in JSON backend This is exported via dump_rtlil command This is read in via ilang_parser
* | | | Merge pull request #2070 from hackfin/masterN. Engelhardt2020-06-041-6/+3
|\ \ \ \ | |_|/ / |/| | | Pyosys API: idict type handling
| * | | idict handling in wrapperMartin2020-05-191-6/+3
| | | | | | | | | | | | | | | | | | | | - Also, re-applied no-line-break workaround to rtlil.h to make parser catch all methods.
* | | | Merge pull request #1862 from boqwxp/cleanup_techmapclairexen2020-05-312-0/+11
|\ \ \ \ | | | | | | | | | | Clean up `passes/techmap/techmap.cc`
| * | | | kernel: Try an order-independent approach to hashing `dict`.Alberto Gonzalez2020-05-191-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Co-Authored-By: David Shah <dave@ds0.me> Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | | | kernel: Ensure `dict` always hashes to the same value given the same contents.Alberto Gonzalez2020-05-141-3/+6
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| * | | | kernel: Re-implement `dict` hash code as a `dict` member function instead of ↵Alberto Gonzalez2020-05-141-20/+14
| | | | | | | | | | | | | | | | | | | | a specialized template for `hash_ops`.
| * | | | techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-142-1/+2
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| * | | | Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-142-6/+21
| | | | | | | | | | | | | | | | | | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
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