iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-145/+80
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-54/+39
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-4/+4
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-25/+25
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-25/+25
*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19	1	-4/+4
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	1	-2/+2
*	Fixed SigPool::del() method	Clifford Wolf	2013-08-06	1	-1/+1
*	Improved auto-detection of -show signals in sat_solve	Clifford Wolf	2013-06-08	1	-0/+24
*	Added additional functionality and cleanups in sigtools.h and celltypes.h	Clifford Wolf	2013-03-15	1	-0/+24
*	Implemented basic functionality of "extract" pass	Clifford Wolf	2013-02-27	1	-0/+14
*	initial import	Clifford Wolf	2013-01-05	1	-0/+415