iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	kernel: const Wire* overload -> Wire* !!!	Eddie Hung	2020-03-26	1	-1/+1
*	kernel: use const reference for SigSet too	Eddie Hung	2020-03-17	1	-18/+18
*	kernel: SigPool to use const& + overloads to prevent implicit SigSpec	Eddie Hung	2020-03-12	1	-19/+25
*	Spacing	Eddie Hung	2019-09-13	1	-1/+1
*	Use template specialisation	Eddie Hung	2019-09-13	1	-2/+9
*	Grammar	Eddie Hung	2019-09-12	1	-1/+1
*	static_assert to enforce this going forward	Eddie Hung	2019-09-12	1	-0/+2
*	SigMap performance improvement	Clifford Wolf	2016-02-01	1	-1/+7
*	Re-added SigMap::allbits()	Clifford Wolf	2015-11-30	1	-0/+9
*	Improved SigMap performance	Clifford Wolf	2015-10-28	1	-5/+8
*	Improvements in new SigMap	Clifford Wolf	2015-10-28	1	-5/+16
*	Removed old SigMap implementation	Clifford Wolf	2015-10-27	1	-224/+0
*	Added hashlib::mfp and new SigMap	Clifford Wolf	2015-10-27	1	-0/+91
*	Added SigMap::allbits()	Clifford Wolf	2015-08-31	1	-0/+8
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-2/+2
*	Added "equiv_induct -undef"	Clifford Wolf	2015-01-31	1	-1/+1
*	dict/pool changes in opt_clean	Clifford Wolf	2014-12-29	1	-0/+9
*	Using Yosys::dict and Yosys::pool in sigtools.h	Clifford Wolf	2014-12-26	1	-4/+7
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-4/+4
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-0/+13
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-3/+5
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-7/+6
*	Added SigPool::check(bit)	Clifford Wolf	2014-07-27	1	-0/+5
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-1/+1
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-1/+1
*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	1	-145/+80
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	1	-2/+2
*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	1	-2/+2
*	SigSpec refactoring: More cleanups of old SigSpec use pattern	Clifford Wolf	2014-07-22	1	-54/+39
*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created...	Clifford Wolf	2014-07-22	1	-4/+4
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-25/+25
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-25/+25
*	Some "const" cleanups in SigMap	Clifford Wolf	2014-07-19	1	-4/+4
*	Some fixes to improve determinism	Clifford Wolf	2013-08-09	1	-2/+2
*	Fixed SigPool::del() method	Clifford Wolf	2013-08-06	1	-1/+1
*	Improved auto-detection of -show signals in sat_solve	Clifford Wolf	2013-06-08	1	-0/+24
*	Added additional functionality and cleanups in sigtools.h and celltypes.h	Clifford Wolf	2013-03-15	1	-0/+24
*	Implemented basic functionality of "extract" pass	Clifford Wolf	2013-02-27	1	-0/+14
*	initial import	Clifford Wolf	2013-01-05	1	-0/+415