| Commit message (Expand) | Author | Age | Files | Lines |
... | |
* | Added module->avail_parameters (for advanced techmap features) | Clifford Wolf | 2013-11-24 | 1 | -0/+1 |
* | Remove auto_wire framework (smarter than the verilog standard) | Clifford Wolf | 2013-11-24 | 1 | -2/+1 |
* | Implemented correct handling of signed module parameters | Clifford Wolf | 2013-11-24 | 1 | -1/+2 |
* | Added more generic _TECHMAP_ wire mechanism to techmap pass | Clifford Wolf | 2013-11-23 | 1 | -0/+6 |
* | Added SigBit struct and refactored RTLIL::SigSpec::extract | Clifford Wolf | 2013-11-22 | 1 | -0/+34 |
* | Major improvements in mem2reg and added "init" sync rules | Clifford Wolf | 2013-11-21 | 1 | -1/+2 |
* | Improved user-friendliness of "sat" and "eval" expression parsing | Clifford Wolf | 2013-11-09 | 1 | -0/+1 |
* | Renamed extend_un0() to extend_u0() and use it in genrtlil | Clifford Wolf | 2013-11-07 | 1 | -1/+1 |
* | Fixed type of sign extension in opt_const $eq/$ne handling | Clifford Wolf | 2013-11-07 | 1 | -0/+1 |
* | Added design->full_selection() helper method | Clifford Wolf | 2013-10-27 | 1 | -0/+3 |
* | Fixed handling of boolean attributes (passes) | Clifford Wolf | 2013-10-24 | 1 | -1/+1 |
* | Fixed handling of boolean attributes (kernel) | Clifford Wolf | 2013-10-24 | 1 | -5/+17 |
* | Changed NEW_WIRE API to return the wire, not the signal | Clifford Wolf | 2013-10-18 | 1 | -1/+1 |
* | Added RTLIL NEW_WIRE macro | Clifford Wolf | 2013-10-18 | 1 | -0/+4 |
* | Added techmap -opt mode | Clifford Wolf | 2013-08-09 | 1 | -2/+5 |
* | Some fixes to improve determinism | Clifford Wolf | 2013-08-09 | 1 | -0/+6 |
* | Added "design" command (-reset, -save, -load) | Clifford Wolf | 2013-07-27 | 1 | -12/+12 |
* | Added "eval" pass | Clifford Wolf | 2013-06-19 | 1 | -0/+1 |
* | Fixed build with clang | Clifford Wolf | 2013-06-18 | 1 | -41/+69 |
* | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 | 1 | -0/+48 |
* | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 1 | -9/+9 |
* | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -0/+2 |
* | Added design->select() api and use it in extract pass | Clifford Wolf | 2013-03-03 | 1 | -0/+7 |
* | Added id2cstr API | Clifford Wolf | 2013-03-01 | 1 | -0/+7 |
* | Do not unescape identifiers starting with \$ | Clifford Wolf | 2013-03-01 | 1 | -1/+1 |
* | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+341 |