| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Added "eval" pass | Clifford Wolf | 2013-06-19 | 1 | -0/+1 |
| * | Fixed build with clang | Clifford Wolf | 2013-06-18 | 1 | -41/+69 |
| * | Added RTLIL::Module::fixup_ports() API and RTLIL::*::rewrite_sigspecs() API | Clifford Wolf | 2013-06-18 | 1 | -0/+48 |
| * | Added "dump" command (part ilang backend) | Clifford Wolf | 2013-06-02 | 1 | -9/+9 |
| * | Improved opt_share for reduce cells | Clifford Wolf | 2013-03-29 | 1 | -0/+2 |
| * | Added design->select() api and use it in extract pass | Clifford Wolf | 2013-03-03 | 1 | -0/+7 |
| * | Added id2cstr API | Clifford Wolf | 2013-03-01 | 1 | -0/+7 |
| * | Do not unescape identifiers starting with \$ | Clifford Wolf | 2013-03-01 | 1 | -1/+1 |
| * | initial import | Clifford Wolf | 2013-01-05 | 1 | -0/+341 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |