iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Made iterators extend std::iterator and added == operator	William Speirs	2014-10-15	1	-2/+4
*	Added support for "keep" on modules	Clifford Wolf	2014-09-29	1	-0/+5
*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19	1	-1/+2
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+0
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-3/+3
*	Added RTLIL::Const::size()	Clifford Wolf	2014-08-31	1	-0/+2
*	Typo fixes in cell->*Param() API	Clifford Wolf	2014-08-31	1	-4/+4
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+11
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	1	-2/+2
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-3/+2
*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19	1	-10/+24
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-0/+3
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	More idstring sort_by_* helpers and fixed tpl ordering in techmap	Clifford Wolf	2014-08-15	1	-1/+13
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-0/+1
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	1	-1/+11
*	Added module->ports	Clifford Wolf	2014-08-14	1	-0/+2
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-4/+2
*	Fixed SigBit(RTLIL::Wire *wire) constructor	Clifford Wolf	2014-08-12	1	-1/+1
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-0/+7
*	Added RTLIL::IdString::in(...)	Clifford Wolf	2014-08-04	1	-5/+18
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-5/+4
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-5/+5
*	More bugfixes related to new RTLIL::IdString	Clifford Wolf	2014-08-02	1	-9/+20
*	Limit size of log_signal buffer to 100 elements	Clifford Wolf	2014-08-02	1	-2/+2
*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	1	-24/+54
*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	1	-13/+84
*	Fixed memory corruption related to id2cstr()	Clifford Wolf	2014-08-02	1	-2/+2
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-62/+35
*	Preparations for RTLIL::IdString redesign: cleanup of existing code	Clifford Wolf	2014-08-02	1	-9/+47
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-5/+5
*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	1	-9/+11
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-4/+11
*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	1	-2/+18
*	Added module->design and cell->module, wire->module pointers	Clifford Wolf	2014-07-31	1	-0/+20
*	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	Clifford Wolf	2014-07-31	1	-14/+4
*	Added techmap CONSTMAP feature	Clifford Wolf	2014-07-30	1	-0/+3
*	Added "kernel/yosys.h" and "kernel/yosys.cc"	Clifford Wolf	2014-07-30	1	-12/+2
*	Added "techmap -map %{design-name}"	Clifford Wolf	2014-07-29	1	-0/+5
*	Added $shift and $shiftx cell types (needed for correct part select behavior)	Clifford Wolf	2014-07-29	1	-8/+14
*	Added wire->upto flag for signals such as "wire [0:7] x;"	Clifford Wolf	2014-07-28	1	-1/+1
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-8/+8
*	Added std::initializer_list<> constructor to SigSpec	Clifford Wolf	2014-07-28	1	-0/+3
*	Added proper Design->addModule interface	Clifford Wolf	2014-07-27	1	-1/+6
*	Added RTLIL::SigSpecConstIterator	Clifford Wolf	2014-07-27	1	-0/+18
*	Added RTLIL::Module::wire(id) and cell(id) lookup functions	Clifford Wolf	2014-07-27	1	-2/+8
*	Added RTLIL::Design::modules()	Clifford Wolf	2014-07-27	1	-0/+3
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Added conversion from ObjRange to std::vector and std::set	Clifford Wolf	2014-07-27	1	-0/+15
*	Added RTLIL::ObjIterator and RTLIL::ObjRange	Clifford Wolf	2014-07-27	1	-1/+88