| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | VCD reader support by using external tool | Miodrag Milanovic | 2022-02-28 | 1 | -0/+19 |
| * | Fix for last clock edge data | Miodrag Milanovic | 2022-02-25 | 1 | -0/+1 |
| * | Changed error message | Miodrag Milanovic | 2022-02-18 | 1 | -1/+1 |
| * | Add support for various ff/latch cells simulation | Miodrag Milanovic | 2022-02-16 | 1 | -98/+43 |
| * | Error detection for co-simulation | Miodrag Milanovic | 2022-02-04 | 1 | -0/+2 |
| * | bug fix and cleanups | Miodrag Milanovic | 2022-02-04 | 1 | -1/+1 |
| * | Cleanup | Miodrag Milanovic | 2022-01-31 | 1 | -1/+0 |
| * | Display simulation time data | Miodrag Milanovic | 2022-01-31 | 1 | -1/+21 |
| * | ignore not found private signals | Miodrag Milanovic | 2022-01-28 | 1 | -2/+1 |
| * | preserve VCD mangled names | Miodrag Milanovic | 2022-01-28 | 1 | -1/+3 |
| * | detect edges even when x | Miodrag Milanovic | 2022-01-28 | 1 | -2/+2 |
| * | cleanup | Miodrag Milanovic | 2022-01-28 | 1 | -13/+1 |
| * | Do actual compare | Miodrag Milanovic | 2022-01-28 | 1 | -65/+41 |
| * | Add more options and time handling | Miodrag Milanovic | 2022-01-28 | 1 | -0/+1 |
| * | Add fstdata helper class | Miodrag Milanovic | 2022-01-26 | 1 | -0/+265 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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