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* kernel: use more ID::*Eddie Hung2020-04-029-142/+142
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-023-38/+44
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-38/+44
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* | Merge pull request #1844 from YosysHQ/dave/gen-source-locDavid Shah2020-04-011-0/+6
|\ \ | | | | | | verilog: Add location info for generate constructs
| * | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
|\ \ \ | | | | | | | | ast: simplify to fully populate dynamic slicing case transformation
| * | | ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
|\ \ \ | |_|/ |/| | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
| * | Add explanatory comment about inefficient wire removal and remove ↵Alberto Gonzalez2020-03-301-4/+8
| | | | | | | | | | | | | | | | | | superfluous call to `fixup_ports()`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
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| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
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* | | Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
|\ \ \ | | | | | | | | Support module/package/interface/block scope for typedef names.
| * | | Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
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| * | | Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
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| * | | Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
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* | | | Merge pull request #1778 from rswarbrick/sv-definesN. Engelhardt2020-03-304-149/+578
|\ \ \ \ | | | | | | | | | | Add support for SystemVerilog-style `define to Verilog frontend
| * | | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | | | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
|\ \ \ \ | |/ / / |/| | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
| * | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this commit, every initial assignment to a memory generated two wires and four assigns in a process. For unknown reasons (I did not investigate), large amounts of assigns cause quadratic slowdown later in the AST frontend, in processAst/removeSignalFromCaseTree. As a consequence, common and reasonable Verilog code, such as: reg [`WIDTH:0] mem [0:`DEPTH]; integer i; initial for (i = 0; i <= `DEPTH; i++) mem[i] = 0; took extremely long time to be processed; around 80 s for a 8-wide, 8192-deep memory. After this commit, initial assignments where address and/or data are constant (after `generate`) do not incur the cost of intermediate wires; expressions like `mem[i+1]=i^(i<<1)` are considered constant. This results in speedups of orders of magnitude for common memory sizes; it now takes merely 0.4 s to process a 8-wide, 8192-deep memory, and only 5.8 s to process a 8-wide, 131072-deep one. As a bonus, this change also results in nontrivial speedups later in the synthesis pipeline, since pass sequencing issues meant that all of these intermediate wires were subject to transformations such as width reduction, even though they existed solely to be constant folded away in `memory_collect`.
* | | | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
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* | | | Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
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* | | | Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
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* | | | Parser changes to support typedef.Peter2020-03-224-10/+88
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* | | | Merge pull request #1788 from YosysHQ/eddie/fix_ndebugEddie Hung2020-03-192-2/+2
|\ \ \ \ | | | | | | | | | | Fix NDEBUG warnings
| * | | | Fix NDEBUG warningsEddie Hung2020-03-192-2/+2
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* | | | | Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
|\ \ \ \ \ | |/ / / / |/| | | | Add dependency to verilog_lexer.cc
| * | | | Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | | | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-192-7/+31
|\ \ \ \ | |/ / / |/| | | Add precise locations for asserts
| * | | Add precise locations for assertshuaixv2020-03-192-7/+31
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* | | | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* | | Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
|\ \ \ | | | | | | | | refixed parsing of constant with comment between size and value
| * | | refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
| | | | | | | | | | | | | | | | | | | | | | | | The three parts of a based constant (size, base, digits) are now three separate tokens, allowing the linear whitespace (including comments) between them to be treated as normal inter-token whitespace.
* | | | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-2/+53
|\ \ \ \ | |_|_|/ |/| | | Set AST node source location in more parser rules.
| * | | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
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| * | | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* / / Fix compilation for emccjiegec2020-03-111-1/+2
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* | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-038-299/+384
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-238-299/+384
| | | | | | | | | | | | and RTLIL nodes.
* | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
|\ \ \ | | | | | | | | verilog: instead of modifying localparam size, extend init constant expr
| * | | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
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* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-12/+20
|\ \ \ | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
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* | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
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* | | Comment out log()Eddie Hung2020-02-271-1/+1
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* | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-213-36/+92
|\ \ | | | | | | Improve specify parser
| * | verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
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| * | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
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| * | verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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