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* kernel: use more ID::*Eddie Hung2020-04-029-142/+142
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-023-38/+44
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| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-38/+44
* | Merge pull request #1844 from YosysHQ/dave/gen-source-locDavid Shah2020-04-011-0/+6
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| * | verilog: Add location info for generate constructsDavid Shah2020-04-011-0/+6
* | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-1/+1
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| * | | ast: simplify to fully populate dynamic slicing case transformationEddie Hung2020-03-311-1/+1
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* | | Merge pull request #1783 from boqwxp/astcc_cleanupEddie Hung2020-03-301-13/+20
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| * | Add explanatory comment about inefficient wire removal and remove superfluous...Alberto Gonzalez2020-03-301-4/+8
| * | Revert over-aggressive change to a more modest cleanup.Alberto Gonzalez2020-03-271-2/+3
| * | Clean up pseudo-private member usage in `frontends/ast/ast.cc`.Alberto Gonzalez2020-03-191-11/+13
* | | Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-304-41/+81
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| * | | Inline productions to follow house style.Peter Crozier2020-03-271-33/+29
| * | | Error duplicate declarations of a typedef name in the same scope.Peter Crozier2020-03-242-3/+11
| * | | Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-234-20/+56
* | | | Merge pull request #1778 from rswarbrick/sv-definesN. Engelhardt2020-03-304-149/+578
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| * | | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-149/+578
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* | | | Merge pull request #1607 from whitequark/simplify-simplify-meminitClaire Wolf2020-03-271-63/+82
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| * | | ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.whitequark2020-02-071-65/+84
* | | | Simplify was not being called for packages. Broke typedef enums.Peter Crozier2020-03-221-5/+8
* | | | Build pkg_user_types before parsing in case of changes in the design.Peter Crozier2020-03-221-6/+3
* | | | Clear pkg_user_types if no packages following a 'design -reset-vlog'.Peter2020-03-222-0/+5
* | | | Parser changes to support typedef.Peter2020-03-224-10/+88
* | | | Merge pull request #1788 from YosysHQ/eddie/fix_ndebugEddie Hung2020-03-192-2/+2
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| * | | | Fix NDEBUG warningsEddie Hung2020-03-192-2/+2
* | | | | Merge pull request #1787 from YosysHQ/mmicko/lexer_depsMiodrag Milanović2020-03-191-1/+1
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| * | | | Add one mode dependencyMiodrag Milanovic2020-03-191-1/+1
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* | | | Merge pull request #1775 from huaixv/asserts_locationsN. Engelhardt2020-03-192-7/+31
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| * | | Add precise locations for assertshuaixv2020-03-192-7/+31
* | | | Add AST node source location information in a couple more parser rules.Alberto Gonzalez2020-03-171-0/+2
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* | | Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-19/+43
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| * | | refixed parsing of constant with comment between size and valueMarcus Comstedt2020-03-112-19/+43
* | | | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-2/+53
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| * | | verilog: also set location for simple_behavioral_stmtEddie Hung2020-03-101-0/+4
| * | | Set AST source locations in more parser rules.Alberto Gonzalez2020-03-101-2/+49
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* / / Fix compilation for emccjiegec2020-03-111-1/+2
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* | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-4/+6
* | Fix bison warning for "pure-parser" optionClaire Wolf2020-03-031-1/+1
* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-038-299/+384
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| * | Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-238-299/+384
* | | Merge pull request #1681 from YosysHQ/eddie/fix1663Claire Wolf2020-03-031-15/+13
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| * | | verilog: instead of modifying localparam size, extend init constant exprEddie Hung2020-02-051-15/+13
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* | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-022-12/+20
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| * | | ast: quiet down when deriving blackbox modulesEddie Hung2020-02-272-12/+20
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* | | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
* | | Comment out log()Eddie Hung2020-02-271-1/+1
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* | Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-213-36/+92
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| * | verilog: add support for more delays than just rise/fallEddie Hung2020-02-191-1/+40
| * | verilog: ignore ranges too without -specifyEddie Hung2020-02-131-1/+2
| * | verilog: improve specify support when not in -specify modeEddie Hung2020-02-131-13/+7
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