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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-025-11/+11
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Add "read_ilang -[no]overwrite"Clifford Wolf2018-12-233-4/+54
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix segfault in AST simplifyClifford Wolf2018-12-181-0/+5
| | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Improve src tagging (using names and attrs) of cells and wires in verific ↵Clifford Wolf2018-12-182-99/+160
| | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at>
* read_ilang: allow slicing sigspecs.whitequark2018-12-161-10/+6
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* verilog_parser: Properly handle recursion when processing attributesSylvain Munaut2018-12-141-19/+29
| | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Verific updatesClifford Wolf2018-12-061-53/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make return value of $clog2 signedSylvain Munaut2018-11-241-1/+1
| | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* Set Verific flag vhdl_support_variable_slice=1Clifford Wolf2018-11-091-0/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Allow square brackets in liberty identifiersClifford Wolf2018-11-051-1/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add warning for SV "restrict" without "property"Clifford Wolf2018-11-041-2/+11
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Various indenting fixes in AST front-end (mostly space vs tab issues)Clifford Wolf2018-11-043-99/+69
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Make and dependent upon LSB onlyZipCPU2018-11-031-2/+8
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* Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵Clifford Wolf2018-11-011-2/+15
| | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix minor typo in error messageClifford Wolf2018-10-251-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-251-14/+14
|\ | | | | More meaningful SystemVerilog/Verilog parser error messages
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-251-14/+14
| | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* | Improve read_verilog range out of bounds warningClifford Wolf2018-10-201-6/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-203-134/+108
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* | Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-3/+105
| | | | | | | | test case
* | Fixed memory leakRuben Undheim2018-10-201-0/+1
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* Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-186-14/+353
|\ | | | | Support for SystemVerilog interfaces and modports
| * Handle FIXME for modport members without type directly in frontRuben Undheim2018-10-131-6/+8
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| * Documentation improvements etc.Ruben Undheim2018-10-132-8/+35
| | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * Fix build error with clangRuben Undheim2018-10-121-1/+1
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| * Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-124-8/+89
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| * Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-126-14/+243
| | | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | Merge pull request #664 from tklam/ignore-verilog-protectClifford Wolf2018-10-181-0/+3
|\ \ | | | | | | Ignore protect endprotect
| * | ignore protect endprotectargama2018-10-161-0/+3
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* | Minor code cleanups in liberty front-endClifford Wolf2018-10-171-16/+5
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #660 from tklam/parse-liberty-detect-ff-latchClifford Wolf2018-10-171-0/+17
|\ \ | | | | | | Handling ff/latch in liberty files
| * | detect ff/latch before processing other nodesargama2018-10-141-0/+17
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* | Merge pull request #638 from udif/pr_reg_wire_errorClifford Wolf2018-10-171-0/+12
|\ \ | |/ |/| Fix issue #630
| * Fixed issue #630 by fixing a minor typo in the previous commitUdi Finkelstein2018-09-251-2/+2
| | | | | | | | (as well as a non critical minor code optimization)
| * Merge branch 'master' into pr_reg_wire_errorUdi Finkelstein2018-09-1821-479/+1448
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| * | Fixed remaining cases where we check fo wire reg/wire incorrect assignmentsUdi Finkelstein2018-09-181-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule
* | | Improve Verific importer blackbox handlingClifford Wolf2018-10-071-2/+14
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix compiler warning in verific.ccClifford Wolf2018-10-051-0/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix for issue 594.Tom Verbeure2018-10-021-1/+2
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* | | Add read_verilog $changed supportDan Gisselquist2018-10-011-1/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosysClifford Wolf2018-09-301-1/+1
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| * | | Fix handling of $past 2nd argument in read_verilogClifford Wolf2018-09-301-1/+1
| | |/ | |/| | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add "read_verilog -noassert -noassume -assert-assumes"Clifford Wolf2018-09-243-6/+49
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵Clifford Wolf2018-09-231-3/+9
|/ / | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "verific -L <int>" optionClifford Wolf2018-09-043-2/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add "make coverage"Clifford Wolf2018-08-276-12/+10
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #610 from udif/udif_specify_round2Clifford Wolf2018-08-231-16/+39
|\ \ | | | | | | More specify/endspecify fixes
| * | Fixed all known specify/endspecify issues, without breaking 'make test'.Udi Finkelstein2018-08-201-12/+12
| | | | | | | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses
| * | Yosys can now parse ↵Udi Finkelstein2018-08-201-10/+22
| | | | | | | | | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value.
| * | A few minor enhancements to specify block parsing.Udi Finkelstein2018-08-151-2/+13
| | | | | | | | | | | | Just remember specify blocks are parsed but ignored.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 21:54:01 +0000