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Age
Files
Lines
*
Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymore
Clifford Wolf
2014-08-23
1
-4
/
+1
|
*
Changed frontend-api from FILE to std::istream
Clifford Wolf
2014-08-23
11
-34
/
+46
|
*
Added emscripten (emcc) support to build system and some build fixes
Clifford Wolf
2014-08-22
2
-1
/
+17
|
*
Added support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf
2014-08-22
1
-0
/
+12
|
*
Archibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf
2014-08-22
1
-6
/
+90
|
*
Fixed small memory leak in ast simplify
Clifford Wolf
2014-08-21
1
-3
/
+3
|
*
Added support for DPI function with different names in C and Verilog
Clifford Wolf
2014-08-21
3
-9
/
+20
|
*
Added AstNode::asInt()
Clifford Wolf
2014-08-21
3
-2
/
+24
|
*
Fixed memory leak in DPI function calls
Clifford Wolf
2014-08-21
1
-0
/
+4
|
*
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf
2014-08-21
8
-3
/
+135
|
*
Added support for global tasks and functions
Clifford Wolf
2014-08-21
3
-27
/
+49
|
*
Added "via_celltype" attribute on task/func
Clifford Wolf
2014-08-18
2
-18
/
+83
|
*
Added const folding of AST_CASE to AST simplifier
Clifford Wolf
2014-08-18
3
-1
/
+41
|
*
Improved AST ProcessGenerator performance
Clifford Wolf
2014-08-17
1
-3
/
+3
|
*
Use stackmap<> in AST ProcessGenerator
Clifford Wolf
2014-08-17
3
-24
/
+22
|
*
Added module->uniquify()
Clifford Wolf
2014-08-16
1
-6
/
+2
|
*
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf
2014-08-16
1
-41
/
+26
|
*
Renamed $_INV_ cell type to $_NOT_
Clifford Wolf
2014-08-15
2
-14
/
+14
|
*
Fixed bug in "read_verilog -ignore_redef"
Clifford Wolf
2014-08-15
1
-1
/
+1
|
*
Added RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf
2014-08-14
1
-11
/
+3
|
*
Changed the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf
2014-08-14
3
-21
/
+31
|
*
Fixed line numbers when using here-doc macros
Clifford Wolf
2014-08-14
1
-4
/
+9
|
*
Fixed handling of task outputs
Clifford Wolf
2014-08-14
1
-2
/
+4
|
*
Added module->ports
Clifford Wolf
2014-08-14
2
-0
/
+2
|
*
Added support for non-standard """ macro bodies
Clifford Wolf
2014-08-13
1
-1
/
+12
|
*
Fixed building verific bindings
Clifford Wolf
2014-08-12
2
-3
/
+3
|
*
Also allow "module foobar(input foo, output bar, ...);" syntax
Clifford Wolf
2014-08-07
1
-3
/
+5
|
*
Added AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf
2014-08-06
4
-5
/
+80
|
*
Improved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf
2014-08-05
3
-9
/
+27
|
*
Fixed AST handling of variables declared inside a functions main block
Clifford Wolf
2014-08-05
1
-3
/
+3
|
*
Added support for non-standard "module mod_name(...);" syntax
Clifford Wolf
2014-08-04
1
-1
/
+7
|
*
More bugfixes related to new RTLIL::IdString
Clifford Wolf
2014-08-02
2
-16
/
+16
|
*
More cleanups related to RTLIL::IdString usage
Clifford Wolf
2014-08-02
1
-6
/
+6
|
*
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf
2014-08-02
2
-3
/
+3
|
*
Replaced sha1 implementation
Clifford Wolf
2014-08-01
1
-27
/
+2
|
*
Fixed build of verific bindings
Clifford Wolf
2014-07-31
1
-11
/
+11
|
*
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf
2014-07-31
3
-85
/
+85
|
*
Added module->design and cell->module, wire->module pointers
Clifford Wolf
2014-07-31
4
-11
/
+11
|
*
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf
2014-07-31
16
-47
/
+108
|
*
Fixed counting verilog line numbers for "// synopsys translate_off" sections
Clifford Wolf
2014-07-30
2
-4
/
+4
|
*
Fixed Verilog pre-processor for files with no trailing newline
Clifford Wolf
2014-07-29
1
-1
/
+1
|
*
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf
2014-07-29
1
-5
/
+11
|
*
Removed left over debug code
Clifford Wolf
2014-07-28
2
-2
/
+0
|
*
Fixed part selects of parameters
Clifford Wolf
2014-07-28
2
-7
/
+31
|
*
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf
2014-07-28
1
-5
/
+31
|
*
Fixed RTLIL code generator for part select of parameter
Clifford Wolf
2014-07-28
1
-2
/
+2
|
*
Fixed width detection for part selects
Clifford Wolf
2014-07-28
1
-2
/
+2
|
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
4
-13
/
+17
|
*
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf
2014-07-28
3
-1
/
+8
|
*
Using log_assert() instead of assert()
Clifford Wolf
2014-07-28
8
-38
/
+32
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