iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Fixed brojen $error()/$info/$warning() on non-generate blocks	Udi Finkelstein	2019-06-11	2	-3/+13
*	Fix spacing from spaces to tabs	Eddie Hung	2019-06-07	1	-362/+362
*	Fix spacing (entire file is wrong anyway, will fix later)	Eddie Hung	2019-06-07	1	-3/+3
*	Remove unnecessary std::getline() for ASCII	Eddie Hung	2019-06-07	1	-3/+0
*	Fix read_aiger -- create zero driver, fix init width, parse 'b'	Eddie Hung	2019-06-07	2	-13/+52
*	Fixes and cleanups in AST_TECALL handling	Clifford Wolf	2019-06-07	3	-46/+34
*	Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...	Clifford Wolf	2019-06-07	6	-5/+64
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\| *	Initial implementation of elaboration system tasks	Udi Finkelstein	2019-05-03	6	-5/+64
* \|	Cleanup tux3-implicit_named_connection	Clifford Wolf	2019-06-07	1	-1/+1
* \|	Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys int...	Clifford Wolf	2019-06-07	1	-1/+10
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\| * \|	SystemVerilog support for implicit named port connections	tux3	2019-06-06	1	-9/+17
* \| \|	Merge pull request #1060 from antmicro/parsing_attr_on_port_conn	Clifford Wolf	2019-06-06	1	-10/+14
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\| * \|	Fixed memory leak.	Maciej Kurc	2019-06-05	1	-0/+4
\| * \|	Added support for parsing attributes on port connections.	Maciej Kurc	2019-05-31	1	-10/+10
* \| \|	Only support Symbiotic EDA flavored Verific	Clifford Wolf	2019-06-02	1	-0/+8
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* \|	Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...	Clifford Wolf	2019-05-30	1	-0/+3
* \|	Merge branch 'master' into wandwor	Stefan Biereigel	2019-05-27	5	-14/+47
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\| * \	Merge pull request #1044 from mmicko/invalid_width_range	Clifford Wolf	2019-05-27	1	-1/+2
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\| \| * \|	Give error instead of asserting for invalid range, fixes #947	Miodrag Milanovic	2019-05-27	1	-1/+2
\| * \| \|	Added support for unsized constants, fixes #1022	Miodrag Milanovic	2019-05-27	5	-13/+45
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* \| \|	remove leftovers from ast data structures	Stefan Biereigel	2019-05-27	2	-4/+0
* \| \|	move wand/wor resolution into hierarchy pass	Stefan Biereigel	2019-05-27	1	-97/+14
* \| \|	fix assignment of non-wires	Stefan Biereigel	2019-05-23	1	-16/+19
* \| \|	fix indentation across files	Stefan Biereigel	2019-05-23	4	-63/+83
* \| \|	implementation for assignments working	Stefan Biereigel	2019-05-23	3	-14/+83
* \| \|	make lexer/parser aware of wand/wor net types	Stefan Biereigel	2019-05-23	3	-2/+10
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* \|	Rename label	Eddie Hung	2019-05-21	1	-6/+5
* \|	Try again	Eddie Hung	2019-05-21	1	-4/+10
* \|	Fix warning	Eddie Hung	2019-05-21	1	-3/+2
* \|	Read bigger Verilog files.	Kaj Tuomi	2019-05-18	1	-1/+1
* \|	Merge pull request #1013 from antmicro/parameter_attributes	Clifford Wolf	2019-05-16	1	-2/+2
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\| * \|	Added support for parsing attributes on parameters in Verilog frontent. Conte...	Maciej Kurc	2019-05-16	1	-2/+2
* \| \|	Make the generated *.tab.hh include all the headers needed to define the union.	Henner Zeller	2019-05-14	2	-2/+18
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* \|	Merge pull request #946 from YosysHQ/clifford/specify	Clifford Wolf	2019-05-06	8	-35/+366
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\| * \|	Add "real" keyword to ilang format	Clifford Wolf	2019-05-06	2	-1/+8
\| * \|	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify	Clifford Wolf	2019-05-06	2	-2/+10
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\| * \| \|	Improve write_verilog specify support	Clifford Wolf	2019-05-04	1	-0/+3
\| * \| \|	Merge remote-tracking branch 'origin/master' into clifford/specify	Eddie Hung	2019-05-03	3	-2/+14
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\| * \| \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	2	-9/+19
\| * \| \| \|	Improve $specrule interface	Clifford Wolf	2019-04-23	1	-20/+18
\| * \| \| \|	Add $specrule cells for $setup/$hold/$skew specify rules	Clifford Wolf	2019-04-23	4	-4/+86
\| * \| \| \|	Allow $specify[23] cells in blackbox modules	Clifford Wolf	2019-04-23	1	-0/+6
\| * \| \| \|	Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...	Clifford Wolf	2019-04-23	1	-2/+2
\| * \| \| \|	Checking and fixing specify cells in genRTLIL	Clifford Wolf	2019-04-23	1	-1/+15
\| * \| \| \|	Un-break default specify parser	Clifford Wolf	2019-04-23	1	-0/+1
\| * \| \| \|	Add specify parser	Clifford Wolf	2019-04-23	4	-33/+243
* \| \| \| \|	Merge pull request #975 from YosysHQ/clifford/fix968	Clifford Wolf	2019-05-06	1	-2/+0
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\| * \ \ \ \	Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968	Clifford Wolf	2019-05-06	5	-4/+15
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\| * \| \| \| \| \|	Re-enable "final loop assignment" feature	Clifford Wolf	2019-05-01	1	-2/+0
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* \| \| \| \| \|	Merge pull request #871 from YosysHQ/verific_import	Clifford Wolf	2019-05-06	2	-26/+71
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