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* Remove vhdl2verilogClifford Wolf2017-10-252-184/+0
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* Remove all PSL support code from verific.ccClifford Wolf2017-10-201-179/+17
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* Add "verific -vlog-libdir"Clifford Wolf2017-10-131-0/+12
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* Add "verific -vlog-incdir" and "verific -vlog-define"Clifford Wolf2017-10-131-0/+35
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* Update Verific READMEClifford Wolf2017-10-131-0/+7
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* Add Verific fairness/liveness supportClifford Wolf2017-10-121-11/+32
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* Merge branch 'master' of github.com:cliffordwolf/yosysClifford Wolf2017-10-101-16/+5
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| * Remove some dead codeClifford Wolf2017-10-101-15/+0
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| * Allow $past, $stable, $rose, $fell in $global_clock blocksClifford Wolf2017-10-101-1/+5
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* | Start work on pre-processor for Verific SVA propertiesClifford Wolf2017-10-101-10/+153
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* Improve handling of Verific errorsClifford Wolf2017-10-051-11/+9
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* Improve Verific error handling, check VHDL static assertsClifford Wolf2017-10-041-11/+25
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* Fix nasty bug in Verific bindingsClifford Wolf2017-10-041-1/+1
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* Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosysClifford Wolf2017-10-032-14/+14
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| * Turned a few member functions into const, esp. dumpAst(), dumpVlog().Udi Finkelstein2017-09-302-14/+14
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* | Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the ↵Udi Finkelstein2017-09-301-3/+5
|/ | | | | | textbook solution (Oreilly 'Flex & Bison' page 189)
* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-291-1/+1
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-17/+17
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-10/+40
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* enable $bits() and $size() functions only when the SystemVerilog flag is ↵Udi Finkelstein2017-09-261-1/+1
| | | | enabled for read_verilog
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-2/+26
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* $size() now works with memories as well!Udi Finkelstein2017-09-261-1/+3
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* Add $size() function. At the moment it works only on expressions, not on ↵Udi Finkelstein2017-09-261-0/+14
| | | | memories.
* Increase maximum LUT size in blifparse to 12 bitsClifford Wolf2017-09-271-1/+1
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* Parse reals as string in JSON front-endClifford Wolf2017-09-261-0/+28
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* Minor coding style fixClifford Wolf2017-09-261-1/+1
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* Merge branch 'master' of https://github.com/combinatorylogic/yosys into ↵Clifford Wolf2017-09-261-41/+69
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| * Adding support for string macros and macros with arguments after includecombinatorylogic2017-09-211-41/+69
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* | Fix ignoring of simulation timings so that invalid module parameters cause ↵Clifford Wolf2017-09-262-4/+2
|/ | | | syntax errors
* json: Parse inout correctly rather than as an outputRobert Ou2017-08-141-0/+1
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* Add merging of "past FFs" to verific importerClifford Wolf2017-07-291-2/+76
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* Add minimal support for PSL in VHDL via VerificClifford Wolf2017-07-281-19/+155
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* Improve Verific HDL language optionsClifford Wolf2017-07-281-4/+4
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* Fix handling of non-user-declared Verific netbusClifford Wolf2017-07-281-2/+3
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* Improve Verific SVA importerClifford Wolf2017-07-271-0/+34
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* Add log_warning_noprefix() API, Use for Verific warnings and errorsClifford Wolf2017-07-271-1/+1
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* Add "verific -import -n" and "verific -import -nosva"Clifford Wolf2017-07-271-14/+36
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* Improve Verific SVA import: negedge and $pastClifford Wolf2017-07-271-6/+49
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* Improve Verific SVA importerClifford Wolf2017-07-271-37/+58
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* Improve Verific bindings (mostly related to SVA)Clifford Wolf2017-07-261-110/+320
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* Improve "help verific" messageClifford Wolf2017-07-251-5/+5
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* Add "verific -extnets"Clifford Wolf2017-07-251-23/+130
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* Improve "verific -all" handlingClifford Wolf2017-07-251-26/+45
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* Add "verific -import -d <dump_file"Clifford Wolf2017-07-241-6/+35
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* Add "verific -import -flatten" and "verific -import -v"Clifford Wolf2017-07-241-107/+164
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* Add "verific -import -k"Clifford Wolf2017-07-221-42/+51
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* Improve docs for verific bindings, add simply sby exampleClifford Wolf2017-07-225-48/+89
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* Fix "read_blif -wideports" handling of cells with wide portsClifford Wolf2017-07-211-3/+33
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* Add a paragraph about pre-defined macros to read_verilog help messageClifford Wolf2017-07-211-0/+4
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* Add attributes and parameter support to JSON front-endClifford Wolf2017-07-101-7/+50
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