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* Header changes so it will compile on VSWilliam Speirs2014-10-172-4/+10
* Wrapped math in int constructorWilliam Speirs2014-10-171-1/+1
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-162-3/+15
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-152-8/+8
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-156-27/+35
* Added make_temp_{file,dir}() and remove_directory() APIsClifford Wolf2014-10-121-18/+8
* Added run_command() api to replace system() and popen()Clifford Wolf2014-10-121-15/+4
* Do not the 'z' modifier in format string (another win32 fix)Clifford Wolf2014-10-111-2/+2
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-113-3/+3
* Disabled vhdl2verilog command for win32 buildsClifford Wolf2014-10-111-0/+5
* Added format __attribute__ to stringf()Clifford Wolf2014-10-101-1/+1
* Renamed SIZE() to GetSize() because of name collision on Win32Clifford Wolf2014-10-105-29/+29
* namespace YosysClifford Wolf2014-09-275-20/+29
* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
* Corrected spelling mistakes found by lintianRuben Undheim2014-09-064-4/+4
* Removed $bu0 cell typeClifford Wolf2014-09-041-5/+5
* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-231-4/+1
* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-2311-34/+46
* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-222-1/+17
* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-221-0/+12
* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-221-6/+90
* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-213-9/+20
* Added AstNode::asInt()Clifford Wolf2014-08-213-2/+24
* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-218-3/+135
* Added support for global tasks and functionsClifford Wolf2014-08-213-27/+49
* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-182-18/+83
* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
* Added module->uniquify()Clifford Wolf2014-08-161-6/+2
* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-14/+14
* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-141-11/+3
* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
* Added module->portsClifford Wolf2014-08-142-0/+2
* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-1/+12
* Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-064-5/+80
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-053-9/+27
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-3/+3