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* Another $clog2 bugfixClifford Wolf2014-09-081-0/+2
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* Fixed $clog2 (off by one error)Clifford Wolf2014-09-061-2/+2
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* Fixed assignment of out-of bounds array elementClifford Wolf2014-09-061-2/+26
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* Corrected spelling mistakes found by lintianRuben Undheim2014-09-064-4/+4
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* Removed $bu0 cell typeClifford Wolf2014-09-041-5/+5
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* Removed compatbility.{h,cc}: Not using open_memstream/fmemopen anymoreClifford Wolf2014-08-231-4/+1
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* Changed frontend-api from FILE to std::istreamClifford Wolf2014-08-2311-34/+46
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* Added emscripten (emcc) support to build system and some build fixesClifford Wolf2014-08-222-1/+17
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* Added support for non-standard <plugin>:<c_name> DPI syntaxClifford Wolf2014-08-221-0/+12
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* Archibald Rust and Clifford Wolf: ffi-based dpi_call()Clifford Wolf2014-08-221-6/+90
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* Fixed small memory leak in ast simplifyClifford Wolf2014-08-211-3/+3
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* Added support for DPI function with different names in C and VerilogClifford Wolf2014-08-213-9/+20
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* Added AstNode::asInt()Clifford Wolf2014-08-213-2/+24
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* Fixed memory leak in DPI function callsClifford Wolf2014-08-211-0/+4
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* Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)Clifford Wolf2014-08-218-3/+135
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* Added support for global tasks and functionsClifford Wolf2014-08-213-27/+49
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* Added "via_celltype" attribute on task/funcClifford Wolf2014-08-182-18/+83
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* Added const folding of AST_CASE to AST simplifierClifford Wolf2014-08-183-1/+41
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* Improved AST ProcessGenerator performanceClifford Wolf2014-08-171-3/+3
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* Use stackmap<> in AST ProcessGeneratorClifford Wolf2014-08-173-24/+22
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* Added module->uniquify()Clifford Wolf2014-08-161-6/+2
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* AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_mapClifford Wolf2014-08-161-41/+26
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* Renamed $_INV_ cell type to $_NOT_Clifford Wolf2014-08-152-14/+14
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* Fixed bug in "read_verilog -ignore_redef"Clifford Wolf2014-08-151-1/+1
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* Added RTLIL::SigSpec::to_sigbit_map()Clifford Wolf2014-08-141-11/+3
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* Changed the AST genWidthRTLIL subst interface to use a std::mapClifford Wolf2014-08-143-21/+31
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* Fixed line numbers when using here-doc macrosClifford Wolf2014-08-141-4/+9
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* Fixed handling of task outputsClifford Wolf2014-08-141-2/+4
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* Added module->portsClifford Wolf2014-08-142-0/+2
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* Added support for non-standard """ macro bodiesClifford Wolf2014-08-131-1/+12
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* Fixed building verific bindingsClifford Wolf2014-08-122-3/+3
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* Also allow "module foobar(input foo, output bar, ...);" syntaxClifford Wolf2014-08-071-3/+5
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* Added AST_MULTIRANGE (arrays with more than 1 dimension)Clifford Wolf2014-08-064-5/+80
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* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-053-9/+27
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* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-3/+3
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* Added support for non-standard "module mod_name(...);" syntaxClifford Wolf2014-08-041-1/+7
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* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-022-16/+16
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* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-021-6/+6
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* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-022-3/+3
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* Replaced sha1 implementationClifford Wolf2014-08-011-27/+2
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* Fixed build of verific bindingsClifford Wolf2014-07-311-11/+11
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* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-313-85/+85
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* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-314-11/+11
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* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-3116-47/+108
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* Fixed counting verilog line numbers for "// synopsys translate_off" sectionsClifford Wolf2014-07-302-4/+4
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* Fixed Verilog pre-processor for files with no trailing newlineClifford Wolf2014-07-291-1/+1
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* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-291-5/+11
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* Removed left over debug codeClifford Wolf2014-07-282-2/+0
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* Fixed part selects of parametersClifford Wolf2014-07-282-7/+31
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* Set results of out-of-bounds static bit/part select to undefClifford Wolf2014-07-281-5/+31
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