Commit message (Collapse) | Author | Age | Files | Lines | |
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* | Add "read_ilang -[no]overwrite" | Clifford Wolf | 2018-12-23 | 3 | -4/+54 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix segfault in AST simplify | Clifford Wolf | 2018-12-18 | 1 | -0/+5 |
| | | | | | | (as proposed by Dan Gisselquist) Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Improve src tagging (using names and attrs) of cells and wires in verific ↵ | Clifford Wolf | 2018-12-18 | 2 | -99/+160 |
| | | | | | | front-end Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | read_ilang: allow slicing sigspecs. | whitequark | 2018-12-16 | 1 | -10/+6 |
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* | verilog_parser: Properly handle recursion when processing attributes | Sylvain Munaut | 2018-12-14 | 1 | -19/+29 |
| | | | | | | Fixes #737 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Verific updates | Clifford Wolf | 2018-12-06 | 1 | -53/+0 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Make return value of $clog2 signed | Sylvain Munaut | 2018-11-24 | 1 | -1/+1 |
| | | | | | | | | As per Verilog 2005 - 17.11.1. Fixes #708 Signed-off-by: Sylvain Munaut <tnt@246tNt.com> | ||||
* | Set Verific flag vhdl_support_variable_slice=1 | Clifford Wolf | 2018-11-09 | 1 | -0/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Allow square brackets in liberty identifiers | Clifford Wolf | 2018-11-05 | 1 | -1/+2 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Add warning for SV "restrict" without "property" | Clifford Wolf | 2018-11-04 | 1 | -2/+11 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Various indenting fixes in AST front-end (mostly space vs tab issues) | Clifford Wolf | 2018-11-04 | 3 | -99/+69 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Make and dependent upon LSB only | ZipCPU | 2018-11-03 | 1 | -2/+8 |
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* | Do not generate "reg assigned in a continuous assignment" warnings for "rand ↵ | Clifford Wolf | 2018-11-01 | 1 | -2/+15 |
| | | | | | | reg" Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Fix minor typo in error message | Clifford Wolf | 2018-10-25 | 1 | -1/+1 |
| | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 1 | -14/+14 |
|\ | | | | | More meaningful SystemVerilog/Verilog parser error messages | ||||
| * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 1 | -14/+14 |
| | | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | ||||
* | | Improve read_verilog range out of bounds warning | Clifford Wolf | 2018-10-20 | 1 | -6/+6 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Refactor code to avoid code duplication + added comments | Ruben Undheim | 2018-10-20 | 3 | -134/+108 |
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* | | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 1 | -3/+105 |
| | | | | | | | | test case | ||||
* | | Fixed memory leak | Ruben Undheim | 2018-10-20 | 1 | -0/+1 |
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* | Merge pull request #659 from rubund/sv_interfaces | Clifford Wolf | 2018-10-18 | 6 | -14/+353 |
|\ | | | | | Support for SystemVerilog interfaces and modports | ||||
| * | Handle FIXME for modport members without type directly in front | Ruben Undheim | 2018-10-13 | 1 | -6/+8 |
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| * | Documentation improvements etc. | Ruben Undheim | 2018-10-13 | 2 | -8/+35 |
| | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport) | ||||
| * | Fix build error with clang | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 4 | -8/+89 |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 6 | -14/+243 |
| | | | | | | | | This time doing the changes mostly in AST before RTLIL generation | ||||
* | | Merge pull request #664 from tklam/ignore-verilog-protect | Clifford Wolf | 2018-10-18 | 1 | -0/+3 |
|\ \ | | | | | | | Ignore protect endprotect | ||||
| * | | ignore protect endprotect | argama | 2018-10-16 | 1 | -0/+3 |
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* | | Minor code cleanups in liberty front-end | Clifford Wolf | 2018-10-17 | 1 | -16/+5 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #660 from tklam/parse-liberty-detect-ff-latch | Clifford Wolf | 2018-10-17 | 1 | -0/+17 |
|\ \ | | | | | | | Handling ff/latch in liberty files | ||||
| * | | detect ff/latch before processing other nodes | argama | 2018-10-14 | 1 | -0/+17 |
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* | | Merge pull request #638 from udif/pr_reg_wire_error | Clifford Wolf | 2018-10-17 | 1 | -0/+12 |
|\ \ | |/ |/| | Fix issue #630 | ||||
| * | Fixed issue #630 by fixing a minor typo in the previous commit | Udi Finkelstein | 2018-09-25 | 1 | -2/+2 |
| | | | | | | | | (as well as a non critical minor code optimization) | ||||
| * | Merge branch 'master' into pr_reg_wire_error | Udi Finkelstein | 2018-09-18 | 21 | -479/+1448 |
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| * | | Fixed remaining cases where we check fo wire reg/wire incorrect assignments | Udi Finkelstein | 2018-09-18 | 1 | -0/+12 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on Yosys-generated assignments. In this case, offending code was: module top(input in, output out); function func; input arg; func = arg; endfunction assign out = func(in); endmodule | ||||
* | | | Improve Verific importer blackbox handling | Clifford Wolf | 2018-10-07 | 1 | -2/+14 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Fix compiler warning in verific.cc | Clifford Wolf | 2018-10-05 | 1 | -0/+2 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Fix for issue 594. | Tom Verbeure | 2018-10-02 | 1 | -1/+2 |
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* | | | Add read_verilog $changed support | Dan Gisselquist | 2018-10-01 | 1 | -1/+4 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Merge branch 'yosys-0.8-rc' of github.com:YosysHQ/yosys | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
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| * | | | Fix handling of $past 2nd argument in read_verilog | Clifford Wolf | 2018-09-30 | 1 | -1/+1 |
| | |/ | |/| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Add "read_verilog -noassert -noassume -assert-assumes" | Clifford Wolf | 2018-09-24 | 3 | -6/+49 |
| | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | | Added support for ommited "parameter" in Verilog-2001 style parameter decl ↵ | Clifford Wolf | 2018-09-23 | 1 | -3/+9 |
|/ / | | | | | | | | | | | in SV mode Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add "verific -L <int>" option | Clifford Wolf | 2018-09-04 | 3 | -2/+16 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Add "make coverage" | Clifford Wolf | 2018-08-27 | 6 | -12/+10 |
| | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
* | | Merge pull request #610 from udif/udif_specify_round2 | Clifford Wolf | 2018-08-23 | 1 | -16/+39 |
|\ \ | | | | | | | More specify/endspecify fixes | ||||
| * | | Fixed all known specify/endspecify issues, without breaking 'make test'. | Udi Finkelstein | 2018-08-20 | 1 | -12/+12 |
| | | | | | | | | | | | | | | | Some the of parser fixes may look strange but they were needed to avoid shift/reduce conflicts, due to the explicit parentheses in path_delay_value, and the mintypmax values without parentheses | ||||
| * | | Yosys can now parse ↵ | Udi Finkelstein | 2018-08-20 | 1 | -10/+22 |
| | | | | | | | | | | | | | | | | | | | | | https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/master/vtr_flow/primitives.v , (specify block ignored). Must use 'read_verilog -defer' due to a parameter not assigned a default value. | ||||
| * | | A few minor enhancements to specify block parsing. | Udi Finkelstein | 2018-08-15 | 1 | -2/+13 |
| | | | | | | | | | | | | Just remember specify blocks are parsed but ignored. | ||||
* | | | Added -no_dump_ptr flag for AST dump options in 'read_verilog' | Udi Finkelstein | 2018-08-23 | 3 | -9/+20 |
| | | | | | | | | | | | | | | | | | | This option disables the memory pointer display. This is useful when diff'ing different dumps because otherwise the node pointers makes every diff line different when the AST content is the same. |