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Age
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*
sv: fix two struct access bugs
Zachary Snow
2021-07-15
3
-1
/
+10
*
rtlil: Make Process handling more uniform with Cell and Wire.
Marcelina Kościelnicka
2021-07-12
2
-6
/
+2
*
Update to latest Verific with extensions for initial assertions
Miodrag Milanovic
2021-07-09
1
-14
/
+9
*
sv: fix a few struct and enum memory leaks
Zachary Snow
2021-07-06
2
-2
/
+11
*
Merge pull request #2835 from YosysHQ/verific_command
Claire Xen
2021-07-05
1
-0
/
+61
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*
Add additional help
Miodrag Milanovic
2021-07-05
1
-0
/
+22
|
*
Support command files in Verific
Miodrag Milanovic
2021-06-16
1
-0
/
+39
*
|
sv: fix up end label checking
Zachary Snow
2021-06-16
1
-7
/
+18
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/
*
verilog: fix leaking of type names in parser
Xiretza
2021-06-14
1
-0
/
+2
*
verilog: fix wildcard port connections leaking memory
Xiretza
2021-06-14
1
-0
/
+1
*
ast: delete wires and localparams after finishing const evaluation
Xiretza
2021-06-14
1
-0
/
+8
*
verilog: fix leaking ASTNodes
Xiretza
2021-06-14
2
-7
/
+15
*
ast: fix error condition causing assert to fail
Xiretza
2021-06-14
1
-2
/
+1
*
verilog: Squash a memory leak.
Marcelina Kościelnicka
2021-06-14
4
-19
/
+14
*
Merge pull request #2817 from YosysHQ/claire/fixemails
Claire Xen
2021-06-09
25
-25
/
+25
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*
Fixing old e-mail addresses and deadnames
Claire Xenia Wolf
2021-06-08
25
-25
/
+25
*
|
verilog: check for module scope identifiers during width detection
Zachary Snow
2021-06-08
3
-13
/
+30
*
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mem2reg: tolerate out of bounds constant accesses
Zachary Snow
2021-06-08
1
-5
/
+42
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/
*
sv: support tasks and functions within packages
Zachary Snow
2021-06-01
3
-2
/
+22
*
verilog: fix case expression sign and width handling
Zachary Snow
2021-05-25
3
-12
/
+49
*
sv: support remaining assignment operators
Zachary Snow
2021-05-25
2
-42
/
+41
*
Change the type of current_module to Module
Rupert Swarbrick
2021-05-13
2
-24
/
+26
*
Use range-based for loop in AST::process
Rupert Swarbrick
2021-05-13
1
-21
/
+21
*
sv: check validity of package end label
Zachary Snow
2021-05-10
1
-0
/
+2
*
blif: Use library cells' start_offset and upto for wideports.
Marcelina Kościelnicka
2021-05-08
1
-10
/
+27
*
Remove duplicates from conns array in JSON front-end, fixes #2736
Claire Xenia Wolf
2021-04-26
1
-0
/
+4
*
verilog: revise hot comment warnings
Zachary Snow
2021-03-30
1
-6
/
+21
*
preproc: Fix up conditional handling.
Marcelina Kościelnicka
2021-03-30
1
-3
/
+17
*
ast: make design available to process_module()
Zachary Snow
2021-03-24
1
-8
/
+8
*
verilog: check entire user type stack for type definition
Xiretza
2021-03-21
1
-6
/
+12
*
sv: allow typenames as function return types
Zachary Snow
2021-03-19
1
-0
/
+6
*
verilog: rebuild user_type_stack from globals before parsing file
Xiretza
2021-03-18
1
-5
/
+21
*
ast: Use better parameter serialization for paramod names.
Marcelina Kościelnicka
2021-03-18
1
-2
/
+25
*
sv: carry over global typedefs from previous files
Zachary Snow
2021-03-17
1
-2
/
+5
*
verilog: fix buf/not primitives with multiple outputs
Xiretza
2021-03-17
1
-4
/
+15
*
verilog: support module scope identifiers in parametric modules
Zachary Snow
2021-03-16
1
-4
/
+8
*
json: Add support for memories.
Marcelina Kościelnicka
2021-03-15
1
-0
/
+46
*
sv: allow globals in one file to depend on globals in another
Zachary Snow
2021-03-12
2
-1
/
+1
*
verilog: disallow overriding global parameters
Zachary Snow
2021-03-11
1
-0
/
+2
*
Merge pull request #2643 from zachjs/fix-param-no-default-log
whitequark
2021-03-08
1
-1
/
+1
|
\
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*
Fix param without default log line
Zachary Snow
2021-03-07
1
-1
/
+1
*
|
verilog: Use proc memory writes in the frontend.
Marcelina Kościelnicka
2021-03-08
4
-29
/
+89
*
|
Add support for memory writes in processes.
Marcelina Kościelnicka
2021-03-08
2
-1
/
+19
|
/
*
Merge pull request #2626 from zachjs/param-no-default
whitequark
2021-03-07
2
-5
/
+48
|
\
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*
sv: support for parameters without default values
Zachary Snow
2021-03-02
2
-5
/
+48
*
|
Merge pull request #2632 from zachjs/width-limit
whitequark
2021-03-07
1
-0
/
+6
|
\
\
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*
|
verilog: impose limit on maximum expression width
Zachary Snow
2021-03-04
1
-0
/
+6
*
|
|
sv: fix some edge cases for unbased unsized literals
Zachary Snow
2021-03-06
2
-1
/
+23
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/
/
*
/
Update README
Claire Xen
2021-03-04
1
-4
/
+4
|
/
*
verilog: fix sizing of ports with int types in module headers
Zachary Snow
2021-03-01
1
-2
/
+3
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