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* verific: also unflatten for 'hierarchy' flow as per @cliffordwolfEddie Hung2020-01-271-0/+3
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* verific: unflatten struct portsEddie Hung2020-01-241-0/+3
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* read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
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* read_aiger: also rename "$0"Eddie Hung2020-01-141-2/+2
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* read_aiger: uniquify wires with $aiger<autoidx> prefixEddie Hung2020-01-132-9/+13
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* read_aiger: make $and/$not/$lut the prefix not suffixEddie Hung2020-01-131-5/+5
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* read_aiger: consistency between ascii and binary; also name latchesEddie Hung2020-01-071-3/+9
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* read_aiger: connect identical signals togetherEddie Hung2020-01-071-0/+1
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* read_aiger: cope with latches and POs with same nameEddie Hung2020-01-071-2/+12
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* read_aiger: default -clk_name to be emptyEddie Hung2020-01-071-1/+1
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* parse_xaiger to not take box_lookupEddie Hung2019-12-312-18/+20
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* parse_xaiger to reorder ports tooEddie Hung2019-12-311-41/+26
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-201-0/+16
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| * Merge pull request #1569 from YosysHQ/eddie/fix_1531Eddie Hung2019-12-191-0/+16
| |\ | | | | | | verilog: preserve size of $genval$-s in for loops
| | * Stray log_dumpEddie Hung2019-12-111-1/+0
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| | * Preserve size of $genval$-s in for loopsEddie Hung2019-12-111-0/+17
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* | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-194-7/+28
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| * | Send people to symbioticeda.com instead of verific.comClifford Wolf2019-12-182-5/+26
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fixed some missing "verilog_" in documentationRodrigo Alejandro Melo2019-12-132-2/+2
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* | aiger frontend to user shorter, $-prefixed, namesEddie Hung2019-12-171-14/+14
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* | Cleanup xaiger, remove unnecessary complexity with inoutEddie Hung2019-12-171-23/+4
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* | read_xaiger to cope with optional '\n' after 'c'Eddie Hung2019-12-171-2/+2
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* | Name inputs/outputs of aiger 'i%d' and 'o%d'Eddie Hung2019-12-131-13/+6
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-062-5/+9
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| * Merge pull request #1551 from whitequark/manual-cell-operandsClifford Wolf2019-12-051-5/+5
| |\ | | | | | | Clarify semantics of comb cells, in particular shifts
| | * kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-5/+5
| | | | | | | | | | | | | | | | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
| * | read_ilang: do bounds checking on bit indicesMarcin Kościelnicki2019-11-271-0/+4
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* | Call abc9 with "&write -n", and parse_xaiger() to copeEddie Hung2019-12-061-92/+85
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* | Do not connect undriven POs to 1'bxEddie Hung2019-12-061-8/+3
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* | Merge branch 'eddie/clkpart' into xaig_dffEddie Hung2019-11-225-18/+88
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| * Add Verific support for SVA nexttime propertiesClifford Wolf2019-11-221-0/+22
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve handling of verific primitives in "verific -import -V" modeClifford Wolf2019-11-221-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add Verific SVA support for "always" propertiesClifford Wolf2019-11-221-5/+15
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * sv: Correct parsing of always_comb, always_ff and always_latchDavid Shah2019-11-212-5/+40
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * Correctly treat empty modules as blackboxes in VerificClifford Wolf2019-11-201-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Do not rename VHDL entities to "entity(impl)" when they are top modulesClifford Wolf2019-11-202-5/+8
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Consistent log message, ignore 's' extensionEddie Hung2019-11-201-2/+3
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* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-11-199-33/+260
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| * Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "verific -L"Clifford Wolf2019-10-241-1/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix parsing of .cname BLIF statementsClifford Wolf2019-10-161-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add .blackbox support to blif front-endClifford Wolf2019-10-161-0/+6
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Use "(id)" instead of "id" for types as temporary hackClifford Wolf2019-10-145-20/+187
| |\ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * frontends/ast: code styleDavid Shah2019-10-031-2/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix typedefs in blocksDavid Shah2019-10-031-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Disambiguate interface portsDavid Shah2019-10-031-3/+19
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| | * sv: Fix memories of typedefsDavid Shah2019-10-031-1/+1
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
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