| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-06-03 | 1 | -0/+11 |
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| | * | Only support Symbiotic EDA flavored Verific | Clifford Wolf | 2019-06-02 | 1 | -0/+8 |
| | * | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ... | Clifford Wolf | 2019-05-30 | 1 | -0/+3 |
| * | | Assert that box_unique_id is indeed unique | Eddie Hung | 2019-06-03 | 1 | -2/+3 |
| * | | Skip internal modules when generating box_unique_id | Eddie Hung | 2019-06-03 | 1 | -0/+1 |
| * | | parse_xaiger to cope with flops | Eddie Hung | 2019-05-31 | 2 | -83/+123 |
| * | | Merge branch 'xaig' into xc7mux | Eddie Hung | 2019-05-31 | 1 | -0/+18 |
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| | * | | Move clean from aigerparse to abc9 | Eddie Hung | 2019-04-23 | 1 | -2/+0 |
| | * | | Tidy up | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| | * | | Revert "Temporarily remove 'r' extension" | Eddie Hung | 2019-04-22 | 1 | -0/+18 |
| * | | | read_xaiger() to name box signals | Eddie Hung | 2019-05-30 | 1 | -4/+8 |
| * | | | Remove whitespace | Eddie Hung | 2019-05-30 | 1 | -1/+0 |
| * | | | Carry in/out to be the last input/output for chains to be preserved | Eddie Hung | 2019-05-30 | 1 | -0/+38 |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-28 | 6 | -15/+61 |
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| | * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 5 | -14/+47 |
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| | | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 |
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| | | | * | | Give error instead of asserting for invalid range, fixes #947 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+2 |
| | | * | | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 5 | -13/+45 |
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| | * | | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 2 | -4/+0 |
| | * | | | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -97/+14 |
| | * | | | fix assignment of non-wires | Stefan Biereigel | 2019-05-23 | 1 | -16/+19 |
| | * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 4 | -63/+83 |
| | * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 3 | -14/+83 |
| | * | | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 3 | -2/+10 |
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| * | | | read_aiger to only clean own design | Eddie Hung | 2019-05-28 | 1 | -0/+6 |
| * | | | Parse "a" extension and boxes from map file | Eddie Hung | 2019-05-27 | 1 | -41/+60 |
| * | | | Remove unused function | Eddie Hung | 2019-05-27 | 1 | -23/+0 |
| * | | | parse_xaiger to not parse symbol table | Eddie Hung | 2019-05-27 | 1 | -64/+0 |
| * | | | Instantiate cell type (from sym file) otherwise 'clean' warnings | Eddie Hung | 2019-05-27 | 1 | -3/+6 |
| * | | | Add 'cinput' and 'coutput' to symbols file for boxes | Eddie Hung | 2019-05-27 | 1 | -0/+35 |
| * | | | Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux | Eddie Hung | 2019-05-23 | 1 | -5/+9 |
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| | * | | Rename label | Eddie Hung | 2019-05-21 | 1 | -6/+5 |
| | * | | Try again | Eddie Hung | 2019-05-21 | 1 | -4/+10 |
| | * | | Fix warning | Eddie Hung | 2019-05-21 | 1 | -3/+2 |
| * | | | Merge remote-tracking branch 'origin/master' into xc7mux | Eddie Hung | 2019-05-21 | 12 | -72/+473 |
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| | * | | Read bigger Verilog files. | Kaj Tuomi | 2019-05-18 | 1 | -1/+1 |
| | * | | Merge pull request #1013 from antmicro/parameter_attributes | Clifford Wolf | 2019-05-16 | 1 | -2/+2 |
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| | | * | | Added support for parsing attributes on parameters in Verilog frontent. Conte... | Maciej Kurc | 2019-05-16 | 1 | -2/+2 |
| | * | | | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 2 | -2/+18 |
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| | * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 8 | -35/+366 |
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| | | * | | Add "real" keyword to ilang format | Clifford Wolf | 2019-05-06 | 2 | -1/+8 |
| | | * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify | Clifford Wolf | 2019-05-06 | 2 | -2/+10 |
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| | | * | | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -0/+3 |
| | | * | | | Merge remote-tracking branch 'origin/master' into clifford/specify | Eddie Hung | 2019-05-03 | 3 | -2/+14 |
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| | | * | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 2 | -9/+19 |
| | | * | | | | Improve $specrule interface | Clifford Wolf | 2019-04-23 | 1 | -20/+18 |
| | | * | | | | Add $specrule cells for $setup/$hold/$skew specify rules | Clifford Wolf | 2019-04-23 | 4 | -4/+86 |
| | | * | | | | Allow $specify[23] cells in blackbox modules | Clifford Wolf | 2019-04-23 | 1 | -0/+6 |
| | | * | | | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom... | Clifford Wolf | 2019-04-23 | 1 | -2/+2 |
| | | * | | | | Checking and fixing specify cells in genRTLIL | Clifford Wolf | 2019-04-23 | 1 | -1/+15 |
