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Merge pull request #1844 from YosysHQ/dave/gen-source-loc
David Shah
2020-04-01
1
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verilog: Add location info for generate constructs
David Shah
2020-04-01
1
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+6
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Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
Claire Wolf
2020-04-01
1
-1
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+1
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ast: simplify to fully populate dynamic slicing case transformation
Eddie Hung
2020-03-31
1
-1
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+1
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Merge pull request #1783 from boqwxp/astcc_cleanup
Eddie Hung
2020-03-30
1
-13
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+20
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Add explanatory comment about inefficient wire removal and remove superfluous...
Alberto Gonzalez
2020-03-30
1
-4
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+8
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Revert over-aggressive change to a more modest cleanup.
Alberto Gonzalez
2020-03-27
1
-2
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+3
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
Alberto Gonzalez
2020-03-19
1
-11
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+13
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Merge pull request #1811 from PeterCrozier/typedef_scope
N. Engelhardt
2020-03-30
4
-41
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+81
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Inline productions to follow house style.
Peter Crozier
2020-03-27
1
-33
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+29
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Error duplicate declarations of a typedef name in the same scope.
Peter Crozier
2020-03-24
2
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+11
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Support module/package/interface/block scope for typedef names.
Peter Crozier
2020-03-23
4
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+56
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Merge pull request #1778 from rswarbrick/sv-defines
N. Engelhardt
2020-03-30
4
-149
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+578
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Add support for SystemVerilog-style `define to Verilog frontend
Rupert Swarbrick
2020-03-27
4
-149
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+578
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Merge pull request #1607 from whitequark/simplify-simplify-meminit
Claire Wolf
2020-03-27
1
-63
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+82
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT.
whitequark
2020-02-07
1
-65
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+84
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Simplify was not being called for packages. Broke typedef enums.
Peter Crozier
2020-03-22
1
-5
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+8
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Build pkg_user_types before parsing in case of changes in the design.
Peter Crozier
2020-03-22
1
-6
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+3
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Clear pkg_user_types if no packages following a 'design -reset-vlog'.
Peter
2020-03-22
2
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+5
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Parser changes to support typedef.
Peter
2020-03-22
4
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+88
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Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
Eddie Hung
2020-03-19
2
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+2
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Fix NDEBUG warnings
Eddie Hung
2020-03-19
2
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+2
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Merge pull request #1787 from YosysHQ/mmicko/lexer_deps
Miodrag Milanović
2020-03-19
1
-1
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+1
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Add one mode dependency
Miodrag Milanovic
2020-03-19
1
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Merge pull request #1775 from huaixv/asserts_locations
N. Engelhardt
2020-03-19
2
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+31
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Add precise locations for asserts
huaixv
2020-03-19
2
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+31
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Add AST node source location information in a couple more parser rules.
Alberto Gonzalez
2020-03-17
1
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+2
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Merge pull request #1759 from zeldin/constant_with_comment_redux
Miodrag Milanović
2020-03-14
2
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+43
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refixed parsing of constant with comment between size and value
Marcus Comstedt
2020-03-11
2
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+43
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Merge pull request #1754 from boqwxp/precise_locations
Miodrag Milanović
2020-03-14
1
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+53
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verilog: also set location for simple_behavioral_stmt
Eddie Hung
2020-03-10
1
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+4
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Set AST source locations in more parser rules.
Alberto Gonzalez
2020-03-10
1
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+49
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Fix compilation for emcc
jiegec
2020-03-11
1
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+2
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Fix partsel expr bit width handling and add test case
Claire Wolf
2020-03-08
1
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+6
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Fix bison warning for "pure-parser" option
Claire Wolf
2020-03-03
1
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+1
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
8
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+384
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Closes #1717. Add more precise Verilog source location information to AST and...
Alberto Gonzalez
2020-02-23
8
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+384
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Merge pull request #1681 from YosysHQ/eddie/fix1663
Claire Wolf
2020-03-03
1
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+13
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verilog: instead of modifying localparam size, extend init constant expr
Eddie Hung
2020-02-05
1
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+13
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Merge pull request #1724 from YosysHQ/eddie/abc9_specify
Eddie Hung
2020-03-02
2
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+20
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ast: quiet down when deriving blackbox modules
Eddie Hung
2020-02-27
2
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+20
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung
2020-02-27
1
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+22
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Comment out log()
Eddie Hung
2020-02-27
1
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+1
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Merge pull request #1703 from YosysHQ/eddie/specify_improve
Eddie Hung
2020-02-21
3
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+92
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verilog: add support for more delays than just rise/fall
Eddie Hung
2020-02-19
1
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+40
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verilog: ignore ranges too without -specify
Eddie Hung
2020-02-13
1
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+2
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verilog: improve specify support when not in -specify mode
Eddie Hung
2020-02-13
1
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+7
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verilog: ignore '&&&' when not in -specify mode
Eddie Hung
2020-02-13
2
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+6
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specify: system timing checks to accept min:typ:max triple
Eddie Hung
2020-02-13
1
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+29
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verilog: fix $specify3 check
Eddie Hung
2020-02-13
1
-7
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+11
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