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Age
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...
*
Fix permissions on verific vdb files
Clifford Wolf
2018-01-28
1
-0
/
+1
*
Fixed handling of synchronous and asynchronous assertion/assumption/cover in ...
Clifford Wolf
2018-01-23
1
-27
/
+29
*
Add support for "yosys -E"
Clifford Wolf
2018-01-07
2
-2
/
+5
*
Merge pull request #479 from Fatsie/latch_without_data
Clifford Wolf
2018-01-05
1
-4
/
+23
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*
Some standard cell libraries include a latch with only set/reset.
Staf Verhaegen
2018-01-03
1
-4
/
+23
*
|
Bugfix in hierarchy handling of blackbox module ports
Clifford Wolf
2018-01-05
2
-2
/
+2
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/
*
Bugfix in verilog_defaults argument parser
Clifford Wolf
2017-12-24
1
-1
/
+1
*
Add support for Verific PRIM_SVA_NOT properties
Clifford Wolf
2017-12-10
1
-10
/
+25
*
Add Verific OPER_SVA_STABLE support
Clifford Wolf
2017-12-10
1
-2
/
+32
*
Refactoring Verific SVA rewriter
Clifford Wolf
2017-12-10
1
-62
/
+70
*
Fix error handling for nested always/initial
Clifford Wolf
2017-12-02
2
-0
/
+5
*
Add Verilog "automatic" keyword (ignored in synthesis)
Clifford Wolf
2017-11-23
2
-13
/
+18
*
Accept real-valued delay values
Clifford Wolf
2017-11-18
1
-0
/
+1
*
Accommodate Windows-style paths during include-file processing.
William D. Jones
2017-11-14
1
-4
/
+20
*
Remove vhdl2verilog
Clifford Wolf
2017-10-25
2
-184
/
+0
*
Remove all PSL support code from verific.cc
Clifford Wolf
2017-10-20
1
-179
/
+17
*
Add "verific -vlog-libdir"
Clifford Wolf
2017-10-13
1
-0
/
+12
*
Add "verific -vlog-incdir" and "verific -vlog-define"
Clifford Wolf
2017-10-13
1
-0
/
+35
*
Update Verific README
Clifford Wolf
2017-10-13
1
-0
/
+7
*
Add Verific fairness/liveness support
Clifford Wolf
2017-10-12
1
-11
/
+32
*
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf
2017-10-10
1
-16
/
+5
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*
Remove some dead code
Clifford Wolf
2017-10-10
1
-15
/
+0
|
*
Allow $past, $stable, $rose, $fell in $global_clock blocks
Clifford Wolf
2017-10-10
1
-1
/
+5
*
|
Start work on pre-processor for Verific SVA properties
Clifford Wolf
2017-10-10
1
-10
/
+153
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/
*
Improve handling of Verific errors
Clifford Wolf
2017-10-05
1
-11
/
+9
*
Improve Verific error handling, check VHDL static asserts
Clifford Wolf
2017-10-04
1
-11
/
+25
*
Fix nasty bug in Verific bindings
Clifford Wolf
2017-10-04
1
-1
/
+1
*
Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys
Clifford Wolf
2017-10-03
2
-14
/
+14
|
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*
Turned a few member functions into const, esp. dumpAst(), dumpVlog().
Udi Finkelstein
2017-09-30
2
-14
/
+14
*
|
Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textboo...
Udi Finkelstein
2017-09-30
1
-3
/
+5
|
/
*
Allow $size and $bits in verilog mode, actually check test case
Clifford Wolf
2017-09-29
1
-1
/
+1
*
$size() now works correctly for all cases!
Udi Finkelstein
2017-09-26
1
-17
/
+17
*
$size() seems to work now with or without the optional parameter.
Udi Finkelstein
2017-09-26
1
-10
/
+40
*
enable $bits() and $size() functions only when the SystemVerilog flag is enab...
Udi Finkelstein
2017-09-26
1
-1
/
+1
*
Added $bits() for memories as well.
Udi Finkelstein
2017-09-26
1
-2
/
+26
*
$size() now works with memories as well!
Udi Finkelstein
2017-09-26
1
-1
/
+3
*
Add $size() function. At the moment it works only on expressions, not on memo...
Udi Finkelstein
2017-09-26
1
-0
/
+14
*
Increase maximum LUT size in blifparse to 12 bits
Clifford Wolf
2017-09-27
1
-1
/
+1
*
Parse reals as string in JSON front-end
Clifford Wolf
2017-09-26
1
-0
/
+28
*
Minor coding style fix
Clifford Wolf
2017-09-26
1
-1
/
+1
*
Merge branch 'master' of https://github.com/combinatorylogic/yosys into combi...
Clifford Wolf
2017-09-26
1
-41
/
+69
|
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*
Adding support for string macros and macros with arguments after include
combinatorylogic
2017-09-21
1
-41
/
+69
*
|
Fix ignoring of simulation timings so that invalid module parameters cause sy...
Clifford Wolf
2017-09-26
2
-4
/
+2
|
/
*
json: Parse inout correctly rather than as an output
Robert Ou
2017-08-14
1
-0
/
+1
*
Add merging of "past FFs" to verific importer
Clifford Wolf
2017-07-29
1
-2
/
+76
*
Add minimal support for PSL in VHDL via Verific
Clifford Wolf
2017-07-28
1
-19
/
+155
*
Improve Verific HDL language options
Clifford Wolf
2017-07-28
1
-4
/
+4
*
Fix handling of non-user-declared Verific netbus
Clifford Wolf
2017-07-28
1
-2
/
+3
*
Improve Verific SVA importer
Clifford Wolf
2017-07-27
1
-0
/
+34
*
Add log_warning_noprefix() API, Use for Verific warnings and errors
Clifford Wolf
2017-07-27
1
-1
/
+1
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