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* Add "read -verific" and "read -noverific"Clifford Wolf2019-03-271-6/+28
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-15/+71
* Fix mem2reg handling of memories with upto data ports, fixes #888Clifford Wolf2019-03-211-1/+10
* Improve "read_verilog -dump_vlog[12]" handling of upto rangesClifford Wolf2019-03-211-3/+6
* Improve read_verilog debug output capabilitiesClifford Wolf2019-03-213-15/+42
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-198-110/+348
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| * fix local name resolution in prefix constructsZachary Snow2019-03-181-1/+5
| * Improve handling of "full_case" attributesClifford Wolf2019-03-141-0/+9
| * Improve handling of memories used in mem index expressions on LHS of an assig...Clifford Wolf2019-03-121-5/+16
| * Remove outdated "blocking assignment to memory" warningClifford Wolf2019-03-121-10/+0
| * Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867Clifford Wolf2019-03-121-6/+8
| * Fix handling of cases that look like sva labels, fixes #862Clifford Wolf2019-03-102-92/+66
| * Merge pull request #858 from YosysHQ/clifford/svalabelsClifford Wolf2019-03-095-56/+201
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| | * Also add support for labels on sva module items, fixes #699Clifford Wolf2019-03-082-44/+113
| | * Add support for SVA labels in read_verilogClifford Wolf2019-03-073-26/+89
| | * Add hack for handling SVA labels via VerificClifford Wolf2019-03-071-1/+14
| * | Update help message for -chparamEddie Hung2019-03-091-1/+2
| * | Add -chparam option to verific commandEddie Hung2019-03-091-2/+18
| * | Fix spellingEddie Hung2019-03-091-1/+1
| * | Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-15/+18
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| * Merge pull request #848 from YosysHQ/clifford/fix763Clifford Wolf2019-03-021-1/+5
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| | * Fix error for wire decl in always block, fixes #763Clifford Wolf2019-03-021-1/+5
| * | Only run derive on blackbox modules when ports have dynamic sizeClifford Wolf2019-03-022-0/+20
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| * Fix $global_clock handling vs autowireClifford Wolf2019-03-021-1/+1
| * Fix $readmem[hb] for mem2reg memories, fixes #785Clifford Wolf2019-03-021-0/+35
| * Use mem2reg on memories that only have constant-index write portsClifford Wolf2019-03-012-0/+13
| * Improve "read" error msgClifford Wolf2019-02-281-1/+1
| * Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+4
| * Check if Verific was built with DB_PRESERVE_INITIAL_VALUEClifford Wolf2019-02-241-0/+4
| * Fixes related to handling of autowires and upto-ranges, fixes #814Clifford Wolf2019-02-212-9/+12
| * Fix handling of expression width in $past, fixes #810Clifford Wolf2019-02-211-1/+1
| * Fix segfault in printing of some internal error messagesClifford Wolf2019-02-211-2/+2
* | Add author nameEddie Hung2019-03-191-0/+1
* | Fix for using POSIX basenameEddie Hung2019-02-191-2/+4
* | Missing OSX headers?Eddie Hung2019-02-171-0/+5
* | read_aiger to ignore line after ands for ascii, not binaryEddie Hung2019-02-171-2/+1
* | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-171-5/+4
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| * Fix sign handling of real constantsClifford Wolf2019-02-131-5/+4
* | Merge branch 'read_aiger' of github.com:eddiehung/yosys into read_aigerEddie Hung2019-02-121-3/+1
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| * | Do not break for constraintsEddie Hung2019-02-111-1/+0
| * | No increment line_count for binary ANDsEddie Hung2019-02-111-1/+1
| * | Do not ignore newline after AND in binary AIGEddie Hung2019-02-111-1/+0
* | | Use module->add{Not,And}Gate() functionsEddie Hung2019-02-121-8/+2
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* | addDff -> addDffGate as per @daveshah1Eddie Hung2019-02-081-1/+1
* | Fix tabulationEddie Hung2019-02-081-28/+28
* | -module_name arg to go before -clk_nameEddie Hung2019-02-081-7/+7
* | Add missing "[options]" to read_blif helpEddie Hung2019-02-081-1/+1
* | Allow module name to be determined by argument tooEddie Hung2019-02-082-14/+44
* | Refactor into AigerReader classEddie Hung2019-02-082-79/+92
* | Parse binary AIG filesEddie Hung2019-02-081-49/+164