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verilog: impose limit on maximum expression width
Zachary Snow
2021-03-04
1
-0
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+6
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sv: fix some edge cases for unbased unsized literals
Zachary Snow
2021-03-06
2
-1
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+23
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Update README
Claire Xen
2021-03-04
1
-4
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+4
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verilog: fix sizing of ports with int types in module headers
Zachary Snow
2021-03-01
1
-2
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+3
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verilog: fix handling of nested ifdef directives
Zachary Snow
2021-03-01
1
-11
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+38
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Merge pull request #2523 from tomverbeure/define_synthesis
Claire Xen
2021-03-01
1
-3
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+12
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Fix indents.
Tom Verbeure
2021-01-04
1
-2
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+2
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Add -nosynthesis flag for read_verilog command.
Tom Verbeure
2021-01-04
1
-3
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+12
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Merge pull request #2615 from zachjs/genrtlil-conflict
whitequark
2021-03-01
1
-12
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+37
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genrtlil: improve name conflict error messaging
Zachary Snow
2021-02-26
1
-12
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+37
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sv: extended support for integer types
Zachary Snow
2021-02-28
2
-39
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+70
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Implement $countones, $isunknown and $onehot{,0}
Michael Singer
2021-02-26
1
-0
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+28
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Implement $countbits function
Michael Singer
2021-02-26
1
-0
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+59
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Extend simplify() recursion warning
Zachary Snow
2021-02-26
1
-1
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+1
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Merge pull request #2554 from hzeller/master
whitequark
2021-02-25
1
-6
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+17
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Provide an integer implementation of decimal_digits().
Henner Zeller
2021-02-01
1
-2
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+9
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Fix digit-formatting calculation for small numbers.
Henner Zeller
2021-01-21
1
-6
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+10
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Fix handling of unique/unique0/priority cases in the frontend.
Marcelina Kościelnicka
2021-02-25
2
-15
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+16
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Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu...
TimRudy
2021-02-24
1
-2
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+7
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frontend: Make helper functions for printing locations.
Marcelina Kościelnicka
2021-02-23
4
-57
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+71
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Merge pull request #2594 from zachjs/func-arg-width
whitequark
2021-02-23
2
-10
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+30
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verilog: fix sizing of constant args for tasks/functions
Zachary Snow
2021-02-21
2
-10
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+30
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frontend: json: parse negative values
Karol Gugala
2021-02-23
1
-2
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+10
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Merge pull request #2586 from zachjs/tern-recurse
whitequark
2021-02-21
3
-19
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+119
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verilog: support recursive functions using ternary expressions
Zachary Snow
2021-02-12
3
-19
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+119
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verilog: error on macro invocations with missing argument lists
Zachary Snow
2021-02-19
1
-1
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+10
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Merge pull request #2574 from dh73/master
Claire Xen
2021-02-15
1
-0
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+5
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Accept disable case for SVA liveness properties.
Diego H
2021-02-04
1
-0
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+5
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Ganulate Verific support
Miodrag Milanovic
2021-02-12
1
-8
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+16
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Merge pull request #2573 from zachjs/repeat-call
whitequark
2021-02-11
2
-72
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+82
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verilog: refactored constant function evaluation
Zachary Snow
2021-02-04
2
-72
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+82
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Merge pull request #2578 from zachjs/genblk-port
Zachary Snow
2021-02-11
1
-4
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+7
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verlog: allow shadowing module ports within generate blocks
Zachary Snow
2021-02-07
1
-4
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+7
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Add missing is_signed to type_atom
Kamil Rakoczy
2021-02-11
1
-4
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+4
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genrtlil: fix signed port connection codegen failures
Zachary Snow
2021-02-05
1
-1
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+5
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Add check of begin/end labels for genblock
Kamil Rakoczy
2021-02-04
1
-0
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+2
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Merge pull request #2529 from zachjs/unnamed-genblk
whitequark
2021-02-04
3
-148
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+169
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verilog: significant block scoping improvements
Zachary Snow
2021-01-31
3
-148
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+169
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Require latest Verific build
Miodrag Milanovic
2021-01-30
1
-1
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+1
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ast: fix dump_vlog display of casex/casez
Marcelina Kościelnicka
2021-01-29
1
-2
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+2
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verilog: strip leading and trailing spaces in macro args
Zachary Snow
2021-01-28
1
-1
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+5
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Merge pull request #2550 from zachjs/macro-arg-spaces
whitequark
2021-01-25
1
-1
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+0
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verilog: allow spaces in macro arguments
Zachary Snow
2021-01-20
1
-1
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+0
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dpi: Support for chandle type
David Shah
2021-01-23
1
-1
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+16
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Allow combination of rand and const modifiers
Zachary Snow
2021-01-21
1
-2
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+10
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Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavor...
Claire Xenia Wolf
2021-01-20
1
-18
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+18
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sv: fix support wire and var data type modifiers
Zachary Snow
2021-01-20
1
-9
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+23
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Fix input/output attributes when resolving typedef of wire
Kamil Rakoczy
2021-01-18
1
-0
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+3
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Parse package user type in module port list
Lukasz Dalek
2021-01-18
1
-30
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+32
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Merge pull request #2518 from zachjs/recursion
whitequark
2021-01-01
2
-8
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+28
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