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* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-284-51/+83
| | | | Fixes #2447.
* Update to latest verificMiodrag Milanovic2021-07-211-3/+3
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* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-165-4/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-153-1/+10
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-122-6/+2
| | | | | | - add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
* Update to latest Verific with extensions for initial assertionsMiodrag Milanovic2021-07-091-14/+9
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* sv: fix a few struct and enum memory leaksZachary Snow2021-07-062-2/+11
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* Merge pull request #2835 from YosysHQ/verific_commandClaire Xen2021-07-051-0/+61
|\ | | | | Support command files in Verific
| * Add additional helpMiodrag Milanovic2021-07-051-0/+22
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| * Support command files in VerificMiodrag Milanovic2021-06-161-0/+39
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* | sv: fix up end label checkingZachary Snow2021-06-161-7/+18
|/ | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* verilog: fix leaking of type names in parserXiretza2021-06-141-0/+2
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* verilog: fix wildcard port connections leaking memoryXiretza2021-06-141-0/+1
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* ast: delete wires and localparams after finishing const evaluationXiretza2021-06-141-0/+8
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* verilog: fix leaking ASTNodesXiretza2021-06-142-7/+15
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* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
| | | | | type2str returns a string that doesn't start with $ or \, so it can't be assigned to an IdString.
* verilog: Squash a memory leak.Marcelina Kościelnicka2021-06-144-19/+14
| | | | That was added in ecc22f7fedfa639482dbc55a05709da85116a60f
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-0925-25/+25
|\ | | | | Fixing old e-mail addresses and deadnames
| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-0825-25/+25
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-083-13/+30
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-081-5/+42
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-013-2/+22
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* verilog: fix case expression sign and width handlingZachary Snow2021-05-253-12/+49
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
* sv: support remaining assignment operatorsZachary Snow2021-05-252-42/+41
| | | | | - Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>= - Unify existing support for: +=, -=, &=, |=, ^=
* Change the type of current_module to ModuleRupert Swarbrick2021-05-132-24/+26
| | | | | | | | | | | The current_module global is needed so that genRTLIL has somewhere to put cells and wires that it generates as it makes sense of expressions that it sees. However, that doesn't actually need to be an AstModule: the Module base class is enough. This patch should cause no functional change, but the point is that it's now possible to call genRTLIL with a module that isn't an AstModule as "current_module". This will be needed for 'bind' support.
* Use range-based for loop in AST::processRupert Swarbrick2021-05-131-21/+21
| | | | | | No functional change: just get rid of the explicit iterator and replace (*it)-> with child->. It's even the same number of characters, but is hopefully a little easier to read.
* sv: check validity of package end labelZachary Snow2021-05-101-0/+2
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* blif: Use library cells' start_offset and upto for wideports.Marcelina Kościelnicka2021-05-081-10/+27
| | | | Fixes #2729.
* Remove duplicates from conns array in JSON front-end, fixes #2736Claire Xenia Wolf2021-04-261-0/+4
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* verilog: revise hot comment warningsZachary Snow2021-03-301-6/+21
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* preproc: Fix up conditional handling.Marcelina Kościelnicka2021-03-301-3/+17
| | | | | Fixes #2710. Fixes #2711.
* ast: make design available to process_module()Zachary Snow2021-03-241-8/+8
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* verilog: check entire user type stack for type definitionXiretza2021-03-211-6/+12
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* sv: allow typenames as function return typesZachary Snow2021-03-191-0/+6
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* verilog: rebuild user_type_stack from globals before parsing fileXiretza2021-03-181-5/+21
| | | | | | | | | | | | This was actually a ticking UB bomb: after running the parser, the type maps contain pointers to children of the current AST, which is recursively deleted after the pass has executed. This leaves the pointers in user_type_stack dangling, which just happened to never be a problem due to another bug that causes typedefs from higher-level type maps to never be considered. Rebuilding the type stack from the design's globals ensures the AstNode pointers are valid.
* ast: Use better parameter serialization for paramod names.Marcelina Kościelnicka2021-03-181-2/+25
| | | | | | | | | | | | Calling log_signal is problematic for several reasons: - with recent changes, empty string is serialized as { }, which violates the "no spaces in IdString" rule - the type (plain / real / signed / string) is dropped, wrongly conflating functionally different values and potentially introducing a subtle elaboration bug Instead, use a custom simple serialization scheme.
* sv: carry over global typedefs from previous filesZachary Snow2021-03-171-2/+5
| | | | | | | This breaks the ability to use a global typename as a standard identifier in a subsequent input file. This is otherwise backwards compatible, including for sources which previously included conflicting typedefs in each input file.
* verilog: fix buf/not primitives with multiple outputsXiretza2021-03-171-4/+15
| | | | | | | | | | | | From IEEE1364-2005, section 7.3 buf and not gates: > These two logic gates shall have one input and one or more outputs. > The last terminal in the terminal list shall connect to the input of the > logic gate, and the other terminals shall connect to the outputs of > the logic gate. yosys does not follow this and instead interprets the first argument as the output, the second as the input and ignores the rest.
* verilog: support module scope identifiers in parametric modulesZachary Snow2021-03-161-4/+8
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* json: Add support for memories.Marcelina Kościelnicka2021-03-151-0/+46
| | | | | | | | | | | | | | Previously, memories were silently discarded by the JSON backend, making round-tripping modules with them crash. Since there are already some users using JSON to implement custom external passes that use memories (and infer width/size from memory ports), let's fix this by just making JSON backend and frontend support memories as first-class objects. Processes are still not supported, and will now cause a hard error. Fixes #1908.
* sv: allow globals in one file to depend on globals in anotherZachary Snow2021-03-122-1/+1
| | | | | | This defers the simplification of globals so that globals in one file may depend on globals in other files. Adds a simplify() call downstream because globals are appended at the end.
* verilog: disallow overriding global parametersZachary Snow2021-03-111-0/+2
| | | | | | It was previously possible to override global parameters on a per-instance basis. This could be dangerous when using positional parameter bindings, hiding oversupplied parameters.
* Merge pull request #2643 from zachjs/fix-param-no-default-logwhitequark2021-03-081-1/+1
|\ | | | | Fix param without default log line
| * Fix param without default log lineZachary Snow2021-03-071-1/+1
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* | verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-084-29/+89
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* | Add support for memory writes in processes.Marcelina Kościelnicka2021-03-082-1/+19
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* Merge pull request #2626 from zachjs/param-no-defaultwhitequark2021-03-072-5/+48
|\ | | | | sv: support for parameters without default values
| * sv: support for parameters without default valuesZachary Snow2021-03-022-5/+48
| | | | | | | | | | | | | | | | | | - Modules with a parameter without a default value will be automatically deferred until the hierarchy pass - Allows for parameters without defaults as module items, rather than just int the `parameter_port_list`, despite being forbidden in the LRM - Check for parameters without defaults that haven't been overriden - Add location info to parameter/localparam declarations
* | Merge pull request #2632 from zachjs/width-limitwhitequark2021-03-071-0/+6
|\ \ | | | | | | verilog: impose limit on maximum expression width
| * | verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
| | | | | | | | | | | | | | | Designs with unreasonably wide expressions would previously get stuck allocating memory forever.
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