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* Added deep recursion warning to AST simplifyClifford Wolf2015-02-201-1/+7
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* Parser support for complex delay expressionsClifford Wolf2015-02-202-8/+21
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* YosysJS stuffClifford Wolf2015-02-191-0/+1
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* Convert floating point cell parameters to stringsClifford Wolf2015-02-181-9/+12
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* Various fixes for memories with offsetsClifford Wolf2015-02-142-6/+5
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* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-144-7/+29
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* Creating $meminit cells in verilog front-endClifford Wolf2015-02-144-33/+57
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* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-142-1/+5
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* Added AstNode::simplify() recursion counterClifford Wolf2015-02-131-2/+10
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* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-101-6/+2
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* Ignore explicit assignments to constants in HDL codeClifford Wolf2015-02-081-0/+14
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* Fixed a bug with autowire bit sizeClifford Wolf2015-02-081-9/+3
| | | | (removed leftover from when we tried to auto-size the wires)
* Added ENABLE_NDEBUG makefile optionsClifford Wolf2015-01-241-0/+2
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* Ignoring more system task and functionsClifford Wolf2015-01-152-2/+4
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* Fixed handling of "input foo; reg [0:0] foo;"Clifford Wolf2015-01-151-0/+7
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* Consolidate "Blocking assignment to memory.." msgs for the same lineClifford Wolf2015-01-151-3/+9
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* Enable bison to be customizedFabio Utzig2015-01-082-2/+2
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* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
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* Fixed memory->start_offset handlingClifford Wolf2015-01-012-6/+10
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* Added global yosys_celltypesClifford Wolf2014-12-291-1/+1
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* dict/pool changes in astClifford Wolf2014-12-293-16/+24
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* Changed more code to dict<> and pool<>Clifford Wolf2014-12-283-6/+6
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* Improved some warning messagesClifford Wolf2014-12-271-6/+18
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* Fixed mem2reg warning messageClifford Wolf2014-12-271-3/+3
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* Added Yosys::{dict,nodict,vector} container typesClifford Wolf2014-12-263-3/+3
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* Renamed extend() to extend_xx(), changed most users to extend_u0()Clifford Wolf2014-12-241-1/+1
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* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-111-3/+15
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* Fixed minor bug in parsing delaysClifford Wolf2014-11-241-1/+4
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* Fixed two minor bugs in constant parsingClifford Wolf2014-11-242-3/+7
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* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-143-6/+14
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* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-121-1/+1
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* Added log_warning() APIClifford Wolf2014-11-094-17/+17
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* Added "ENABLE_PLUGINS := 0" to verific amd64 build instructionsClifford Wolf2014-11-081-0/+1
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* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-301-4/+5
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* AST simplifier: optimize constant AST_CASE nodes before recursively descendingClifford Wolf2014-10-291-31/+35
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* Added support for task and function args in parenthesesClifford Wolf2014-10-271-6/+45
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* Improvements in $readmem[bh] implementationClifford Wolf2014-10-261-8/+13
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* Added support for $readmemh/$readmembClifford Wolf2014-10-262-0/+113
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* Fixed constant "cond ? string1 : string2" with strings of different sizeClifford Wolf2014-10-251-0/+2
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* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-233-15/+5
| | | | (f.read() + f.gcount() made problems with lines > 16kB)
* minor indenting correctionsClifford Wolf2014-10-191-2/+2
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* Builds on Mac 10.9.2 with LLVM 3.5.Parviz Palangpour2014-10-191-0/+5
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* Fixed various VS warningsClifford Wolf2014-10-181-1/+1
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* Header changes so it will compile on VSWilliam Speirs2014-10-172-4/+10
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* Wrapped math in int constructorWilliam Speirs2014-10-171-1/+1
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* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
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* Fixed handling of invalid array access in mem2reg codeClifford Wolf2014-10-162-3/+15
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* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-152-8/+8
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* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
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* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-156-27/+35
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