| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1163 from whitequark/more-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -0/+1 |
| | | | | More support for case rule attributes | ||||
| * | Merge pull request #1162 from whitequark/rtlil-case-attrs | Clifford Wolf | 2019-07-09 | 1 | -4/+9 |
| | | | | Allow attributes on individual switch cases in RTLIL | ||||
| * | Merge pull request #1147 from YosysHQ/clifford/fix1144 | Clifford Wolf | 2019-07-09 | 1 | -81/+14 |
| | | | | Improve specify dummy parser | ||||
| * | Fix read_verilog assert/assume/etc on default case label, fixes ↵ | Clifford Wolf | 2019-07-09 | 1 | -0/+2 |
| | | | | | | | YosysHQ/SymbiYosys#53 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131 | Clifford Wolf | 2019-06-26 | 1 | -1/+1 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Add upto and offset to JSON ports | Miodrag Milanovic | 2019-06-21 | 1 | -0/+12 |
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| * | Fix typo | Miodrag Milanovic | 2019-06-21 | 1 | -1/+1 |
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| * | Added JSON upto and offset | Clifford Wolf | 2019-06-21 | 1 | -0/+12 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge pull request #1119 from YosysHQ/eddie/fix1118 | Clifford Wolf | 2019-06-21 | 1 | -0/+1 |
| |\ | | | | | Make genvar a signed type | ||||
| | * | Make genvar a signed type | Eddie Hung | 2019-06-20 | 1 | -0/+1 |
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| * | | Maintain "is_unsized" state of constants | Eddie Hung | 2019-06-20 | 1 | -6/+6 |
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| * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵ | Clifford Wolf | 2019-06-20 | 1 | -1/+7 |
| |\ | | | | | | | towoe-unpacked_arrays | ||||
| | * | Unpacked array declaration using size | Tobias Wölfel | 2019-06-19 | 1 | -1/+7 |
| | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work. | ||||
| * | | Add "read_verilog -pwires" feature, closes #1106 | Clifford Wolf | 2019-06-19 | 5 | -9/+44 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add defaultvalue attribute | Clifford Wolf | 2019-06-19 | 1 | -0/+11 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fix handling of "logic" variables with initial value | Clifford Wolf | 2019-06-19 | 1 | -2/+2 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Fixed brojen $error()/$info/$warning() on non-generate blocks | Udi Finkelstein | 2019-06-11 | 2 | -3/+13 |
| |/ | | | | (within always/initial blocks) | ||||
| * | Fix spacing from spaces to tabs | Eddie Hung | 2019-06-07 | 1 | -362/+362 |
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| * | Fix spacing (entire file is wrong anyway, will fix later) | Eddie Hung | 2019-06-07 | 1 | -3/+3 |
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| * | Remove unnecessary std::getline() for ASCII | Eddie Hung | 2019-06-07 | 1 | -3/+0 |
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| * | Fix read_aiger -- create zero driver, fix init width, parse 'b' | Eddie Hung | 2019-06-07 | 2 | -13/+52 |
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| * | Fixes and cleanups in AST_TECALL handling | Clifford Wolf | 2019-06-07 | 3 | -46/+34 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵ | Clifford Wolf | 2019-06-07 | 6 | -5/+64 |
| |\ | | | | | | | clifford/pr983 | ||||
| | * | Initial implementation of elaboration system tasks | Udi Finkelstein | 2019-05-03 | 6 | -5/+64 |
| | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen. | ||||
| * | | Cleanup tux3-implicit_named_connection | Clifford Wolf | 2019-06-07 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵ | Clifford Wolf | 2019-06-07 | 1 | -1/+10 |
| |\ \ | | | | | | | | | | into tux3-implicit_named_connection | ||||
| | * | | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -9/+17 |
| | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | ||||
| * | | | Merge pull request #1060 from antmicro/parsing_attr_on_port_conn | Clifford Wolf | 2019-06-06 | 1 | -10/+14 |
| |\ \ \ | |/ / |/| | | Added support for parsing attributes on port connections. | ||||
| | * | | Fixed memory leak. | Maciej Kurc | 2019-06-05 | 1 | -0/+4 |
| | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| | * | | Added support for parsing attributes on port connections. | Maciej Kurc | 2019-05-31 | 1 | -10/+10 |
| | | | | | | | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | | | Only support Symbiotic EDA flavored Verific | Clifford Wolf | 2019-06-02 | 1 | -0/+8 |
| |/ / | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ↵ | Clifford Wolf | 2019-05-30 | 1 | -0/+3 |
| | | | | | | | | | | | | | fixes #1055 Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge branch 'master' into wandwor | Stefan Biereigel | 2019-05-27 | 5 | -14/+47 |
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| | * \ | Merge pull request #1044 from mmicko/invalid_width_range | Clifford Wolf | 2019-05-27 | 1 | -1/+2 |
| | |\ \ | | | | | | | | | Give error instead of asserting for invalid range, fixes #947 | ||||
| | | * | | Give error instead of asserting for invalid range, fixes #947 | Miodrag Milanovic | 2019-05-27 | 1 | -1/+2 |
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| | * | | | Added support for unsized constants, fixes #1022 | Miodrag Milanovic | 2019-05-27 | 5 | -13/+45 |
| | |/ / | | | | | | | | | | Includes work from @sumit0190 and @AaronKel | ||||
| * | | | remove leftovers from ast data structures | Stefan Biereigel | 2019-05-27 | 2 | -4/+0 |
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| * | | | move wand/wor resolution into hierarchy pass | Stefan Biereigel | 2019-05-27 | 1 | -97/+14 |
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| * | | | fix assignment of non-wires | Stefan Biereigel | 2019-05-23 | 1 | -16/+19 |
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| * | | | fix indentation across files | Stefan Biereigel | 2019-05-23 | 4 | -63/+83 |
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| * | | | implementation for assignments working | Stefan Biereigel | 2019-05-23 | 3 | -14/+83 |
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| * | | | make lexer/parser aware of wand/wor net types | Stefan Biereigel | 2019-05-23 | 3 | -2/+10 |
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| * | | Rename label | Eddie Hung | 2019-05-21 | 1 | -6/+5 |
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| * | | Try again | Eddie Hung | 2019-05-21 | 1 | -4/+10 |
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| * | | Fix warning | Eddie Hung | 2019-05-21 | 1 | -3/+2 |
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| * | | Read bigger Verilog files. | Kaj Tuomi | 2019-05-18 | 1 | -1/+1 |
| | | | | | | | | | Hit parser limit with 3M gate design. This commit fix it. | ||||
| * | | Merge pull request #1013 from antmicro/parameter_attributes | Clifford Wolf | 2019-05-16 | 1 | -2/+2 |
| |\ \ | | | | | | | Support for attributes on parameters and localparams for Verilog frontend | ||||
| | * | | Added support for parsing attributes on parameters in Verilog frontent. ↵ | Maciej Kurc | 2019-05-16 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | Content of those attributes is ignored. Signed-off-by: Maciej Kurc <mkurc@antmicro.com> | ||||
| * | | | Make the generated *.tab.hh include all the headers needed to define the union. | Henner Zeller | 2019-05-14 | 2 | -2/+18 |
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| * | | Merge pull request #946 from YosysHQ/clifford/specify | Clifford Wolf | 2019-05-06 | 8 | -35/+366 |
| |\ \ | | | | | | | Add specify parser | ||||
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index : iCE40/yosys | |
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