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* Added "autoidx" statement to ilang file formatClifford Wolf2014-07-212-25/+10
* Replaced depricated NEW_WIRE macro with module->addWire() callsClifford Wolf2014-07-211-10/+10
* Removed deprecated module->new_wire()Clifford Wolf2014-07-211-5/+5
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-2/+26
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+9
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-9/+36
* Added "inout" ports support to read_libertyClifford Wolf2014-07-161-1/+6
* Set blackbox attribute in "read_liberty -lib"Clifford Wolf2014-07-161-0/+3
* Fixed spelling of "direction" in read_liberty messagesClifford Wolf2014-07-161-2/+2
* changes in verilog frontend for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-162-7/+6
* Added passing of various options to vhdl2verilogClifford Wolf2014-07-121-5/+36
* Fixed processing of initial values for block-local variablesClifford Wolf2014-07-111-0/+5
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-021-0/+7
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-0/+16
* More found_real-related fixes to AstNode::detectSignWidthWorkerClifford Wolf2014-06-241-6/+6
* fixed signdness detection for expressions with realsClifford Wolf2014-06-211-2/+8
* Added AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-172-0/+23
* Improved handling of relational op of real valuesClifford Wolf2014-06-171-8/+9
* Improved ternary support for real valuesClifford Wolf2014-06-161-13/+24
* Use undef (x/z vs. NaN) rules for real values from IEEE Std 1800-2012Clifford Wolf2014-06-162-0/+11
* Fixed parsing of TOK_INTEGER (implies TOK_SIGNED)Clifford Wolf2014-06-161-5/+11
* Added found_real feature to AstNode::detectSignWidthClifford Wolf2014-06-162-6/+11
* Improved AstNode::realAsConst for large numbersClifford Wolf2014-06-151-1/+1
* Improved parsing of large integer constantsClifford Wolf2014-06-151-11/+28
* Improved AstNode::asReal for large integersClifford Wolf2014-06-152-10/+13
* improved (fixed) conversion of real values to bit vectorsClifford Wolf2014-06-144-11/+30
* Fixed relational operators for const real expressionsClifford Wolf2014-06-141-8/+8
* Added support for math functionsClifford Wolf2014-06-141-0/+70
* Added handling of real-valued parameters/localparamsClifford Wolf2014-06-144-24/+62
* Implemented more real arithmeticClifford Wolf2014-06-141-27/+70
* Implemented basic real arithmeticClifford Wolf2014-06-143-6/+51
* Added real->int convertion in ast genrtlilClifford Wolf2014-06-141-0/+12
* Added Verilog lexer and parser support for real valuesClifford Wolf2014-06-134-3/+31
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-124-3/+37
* Add support for cell arraysClifford Wolf2014-06-074-0/+34
* Added support for repeat stmt in const functionsClifford Wolf2014-06-071-0/+19
* further improved const function supportClifford Wolf2014-06-073-17/+22
* made the generate..endgenrate keywords optionalClifford Wolf2014-06-061-4/+8
* improved const function supportClifford Wolf2014-06-063-5/+41
* fix functions with no block (but single statement, loop, etc.)Clifford Wolf2014-06-061-11/+4
* improved ast simplify of const functionsClifford Wolf2014-06-061-7/+28
* added while and repeat support to verilog parserClifford Wolf2014-06-064-1/+31
* Improved error message for options after front-end filename argumentsClifford Wolf2014-06-041-1/+1
* new flags -ignore_miss_func and -ignore_miss_dir for read_libertyJohann Glaser2014-05-281-4/+40
* Fixed clang -Wdeprecated-register warningsClifford Wolf2014-04-202-0/+12
* Replaced depricated %name-prefix= bison directiveClifford Wolf2014-04-202-2/+2
* Fixed mapping of Verific WIDE_DFFRS operatorClifford Wolf2014-03-201-2/+2
* Fixed mapping of Verific FADD primitive with unconnected outputsClifford Wolf2014-03-201-4/+5
* Progress in Verific bindingsClifford Wolf2014-03-171-8/+51
* Progress in Verific bindingsClifford Wolf2014-03-171-5/+50