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* Merge pull request #1060 from antmicro/parsing_attr_on_port_connClifford Wolf2019-06-061-10/+14
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| * Fixed memory leak.Maciej Kurc2019-06-051-0/+4
| * Added support for parsing attributes on port connections.Maciej Kurc2019-05-311-10/+10
* | Only support Symbiotic EDA flavored VerificClifford Wolf2019-06-021-0/+8
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* Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, ...Clifford Wolf2019-05-301-0/+3
* Merge branch 'master' into wandworStefan Biereigel2019-05-275-14/+47
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| * Merge pull request #1044 from mmicko/invalid_width_rangeClifford Wolf2019-05-271-1/+2
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| | * Give error instead of asserting for invalid range, fixes #947Miodrag Milanovic2019-05-271-1/+2
| * | Added support for unsized constants, fixes #1022Miodrag Milanovic2019-05-275-13/+45
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* | remove leftovers from ast data structuresStefan Biereigel2019-05-272-4/+0
* | move wand/wor resolution into hierarchy passStefan Biereigel2019-05-271-97/+14
* | fix assignment of non-wiresStefan Biereigel2019-05-231-16/+19
* | fix indentation across filesStefan Biereigel2019-05-234-63/+83
* | implementation for assignments workingStefan Biereigel2019-05-233-14/+83
* | make lexer/parser aware of wand/wor net typesStefan Biereigel2019-05-233-2/+10
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* Rename labelEddie Hung2019-05-211-6/+5
* Try againEddie Hung2019-05-211-4/+10
* Fix warningEddie Hung2019-05-211-3/+2
* Read bigger Verilog files.Kaj Tuomi2019-05-181-1/+1
* Merge pull request #1013 from antmicro/parameter_attributesClifford Wolf2019-05-161-2/+2
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| * Added support for parsing attributes on parameters in Verilog frontent. Conte...Maciej Kurc2019-05-161-2/+2
* | Make the generated *.tab.hh include all the headers needed to define the union.Henner Zeller2019-05-142-2/+18
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* Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-068-35/+366
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| * Add "real" keyword to ilang formatClifford Wolf2019-05-062-1/+8
| * Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specifyClifford Wolf2019-05-062-2/+10
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| * | Improve write_verilog specify supportClifford Wolf2019-05-041-0/+3
| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-033-2/+14
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| * | | Improve $specrule interfaceClifford Wolf2019-04-232-9/+19
| * | | Improve $specrule interfaceClifford Wolf2019-04-231-20/+18
| * | | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-234-4/+86
| * | | Allow $specify[23] cells in blackbox modulesClifford Wolf2019-04-231-0/+6
| * | | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nom...Clifford Wolf2019-04-231-2/+2
| * | | Checking and fixing specify cells in genRTLILClifford Wolf2019-04-231-1/+15
| * | | Un-break default specify parserClifford Wolf2019-04-231-0/+1
| * | | Add specify parserClifford Wolf2019-04-234-33/+243
* | | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-2/+0
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| * \ \ \ Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-065-4/+15
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| * | | | | Re-enable "final loop assignment" featureClifford Wolf2019-05-011-2/+0
* | | | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-062-26/+71
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| * | | | | For hier_tree::Elaborate() also include SV root modules (bind)Eddie Hung2019-05-031-23/+36
| * | | | | Fix verific_parameters construction, use attribute to mark top netlistsEddie Hung2019-05-032-8/+12
| * | | | | WIP -chparam support for hierarchy when verificEddie Hung2019-05-032-12/+17
| * | | | | verific_import() changes to avoid ElaborateAll()Eddie Hung2019-05-031-15/+38
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* | | | | Fix the other bison warning in ilang_parser.yClifford Wolf2019-05-061-1/+1
* | | | | verilog_parser: Fix Bison warningBen Widawsky2019-05-051-1/+1
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* | | | Merge pull request #988 from YosysHQ/clifford/fix987Clifford Wolf2019-05-042-1/+5
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| * | | | Add approximate support for SV "var" keyword, fixes #987Clifford Wolf2019-05-042-1/+5
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* / / / Add support for SVA "final" keywordClifford Wolf2019-05-042-1/+5
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* | | Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+1
* | | Fix width detection of memory access with bit slice, fixes #974Clifford Wolf2019-05-011-0/+2
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