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* Small improvements in Verilog front-end docsClifford Wolf2016-05-201-0/+3
* Added "yosys -D" featureClifford Wolf2016-04-211-1/+1
* Fixed handling of parameters and const functions in casex/casez patternClifford Wolf2016-04-211-2/+6
* Fixed Verilog parser fix and more similar improvementsClifford Wolf2016-03-151-18/+9
* Use left-recursive rule for cell_port_list in Verilog parser.Andrew Becker2016-03-151-6/+10
* Fixed typos in verilog_defaults help messageClifford Wolf2016-03-101-3/+3
* Fixed handling of parameters and localparams in functionsClifford Wolf2015-11-111-1/+1
* Fixed bug in verilog parserClifford Wolf2015-10-151-1/+1
* SystemVerilog also has assume(), added implicit -D FORMALClifford Wolf2015-10-133-4/+5
* Added support for "parameter" and "localparam" in global contextClifford Wolf2015-10-071-0/+2
* Added read_verilog -nodpiClifford Wolf2015-09-231-0/+19
* Fixed support for $write system taskClifford Wolf2015-09-231-1/+1
* Fixed detection of "task foo(bar);" syntax errorClifford Wolf2015-09-221-0/+2
* Fixed segfault on invalid verilog constant 1'b_Clifford Wolf2015-09-221-1/+1
* Small corrections to const2ast warning messagesClifford Wolf2015-08-171-2/+2
* Check base-n literals only contain valid digitsFlorian Zeitz2015-08-171-0/+3
* Warn on literals exceeding the specified bit widthFlorian Zeitz2015-08-171-34/+39
* Another block of spelling fixesLarry Doolittle2015-08-142-3/+3
* Re-created command-reference-manual.tex, copied some doc fixes to online helpClifford Wolf2015-08-141-6/+6
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Adjust makefiles to work with out-of-tree buildsClifford Wolf2015-08-123-4/+6
* Fixed handling of [a-fxz?] in decimal constantsClifford Wolf2015-08-111-2/+7
* Add -noautowire option to verilog frontendMarcus Comstedt2015-08-011-1/+8
* Fixed trailing whitespacesClifford Wolf2015-07-026-16/+16
* Verilog front-end: define `BLACKBOX in -lib modeClifford Wolf2015-04-191-1/+2
* Ignore celldefine directive in verilog front-endClifford Wolf2015-03-251-0/+3
* Added non-std verilog assume() statementClifford Wolf2015-02-264-5/+25
* Parser support for complex delay expressionsClifford Wolf2015-02-201-7/+20
* YosysJS stuffClifford Wolf2015-02-191-0/+1
* Added "read_verilog -nomeminit" and "nomeminit" attributeClifford Wolf2015-02-141-1/+15
* Fixed handling of "//" in filenames in verilog pre-processorClifford Wolf2015-02-142-1/+5
* Improved read_verilog support for empty behavioral statementsClifford Wolf2015-02-101-6/+2
* Ignoring more system task and functionsClifford Wolf2015-01-151-1/+1
* Enable bison to be customizedFabio Utzig2015-01-081-1/+1
* Define YOSYS and SYNTHESIS in preprocClifford Wolf2015-01-021-1/+2
* Improved some warning messagesClifford Wolf2014-12-271-6/+18
* Fixed supply0/supply1 with many wiresClifford Wolf2014-12-111-3/+15
* Fixed minor bug in parsing delaysClifford Wolf2014-11-241-1/+4
* Fixed two minor bugs in constant parsingClifford Wolf2014-11-242-3/+7
* Added warning for use of 'z' constants in HDLClifford Wolf2014-11-143-6/+14
* Fixed parsing of nested verilog concatenation and replicateClifford Wolf2014-11-121-1/+1
* Added log_warning() APIClifford Wolf2014-11-091-6/+6
* Fixed parsing of "module mymod #( parameter foo = 1, bar = 2 ..."Clifford Wolf2014-10-301-4/+5
* Added support for task and function args in parenthesesClifford Wolf2014-10-271-6/+45
* Re-introduced Yosys::readsome() helper functionClifford Wolf2014-10-232-10/+4
* Print "SystemVerilog" in "read_verilog -sv" log messagesClifford Wolf2014-10-161-1/+1
* Updated .gitignore file for ilang and verilog frontendsClifford Wolf2014-10-151-4/+4
* Replaced readsome() with read() and gcount()Clifford Wolf2014-10-151-3/+5
* Updated lexers & parsers to include prefixesWilliam Speirs2014-10-153-14/+18
* Fixed win32 troubles with f.readsome()Clifford Wolf2014-10-112-2/+2
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