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* Merge pull request #2529 from zachjs/unnamed-genblkwhitequark2021-02-041-17/+28
|\ | | | | verilog: significant block scoping improvements
| * verilog: significant block scoping improvementsZachary Snow2021-01-311-17/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* | verilog: strip leading and trailing spaces in macro argsZachary Snow2021-01-281-1/+5
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* Merge pull request #2550 from zachjs/macro-arg-spaceswhitequark2021-01-251-1/+0
|\ | | | | verilog: allow spaces in macro arguments
| * verilog: allow spaces in macro argumentsZachary Snow2021-01-201-1/+0
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* | Allow combination of rand and const modifiersZachary Snow2021-01-211-2/+10
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* | sv: fix support wire and var data type modifiersZachary Snow2021-01-201-9/+23
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* Parse package user type in module port listLukasz Dalek2021-01-181-30/+32
| | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* sv: complete support for implied task/function port directionsZachary Snow2020-12-311-0/+10
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* Fix SYNTHESIS always being defined in Verilog frontendgeorgerennie2020-12-012-1/+3
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* Ignore empty parameters in Verilog module instantiationsClaire Xenia Wolf2020-10-011-0/+3
| | | | | | Fixes #2394 Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
* Rewrite multirange arrays sizes [n] as [n-1:0]Lukasz Dalek2020-08-031-2/+11
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Treat all bison warnings as errors in verilog front-endClaire Wolf2020-07-151-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Use %precedence in verilog_parser.yClaire Wolf2020-07-151-4/+4
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Fix bison warnings for missing %emptyClaire Wolf2020-07-151-59/+52
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Run bison with -Wall for verilog front-endClaire Wolf2020-07-151-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* Add missing semicolonsKamil Rakoczy2020-07-151-5/+5
| | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix S/R conflictsKamil Rakoczy2020-07-101-1/+2
| | | | | | This commit fixes S/R conflicts introduced by commit 6f9be93. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Fix R/R conflictsKamil Rakoczy2020-07-101-10/+1
| | | | | | | This commit fixes R/R conflicts introduced by commit 7e83a51. Parameter logic is already defined as part of `param_range_type` rule. Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-101-10/+19
| | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* verilog_parser: turn S/R and R/R conflicts into hard errors.whitequark2020-07-091-1/+1
| | | | Fixes #2253.
* Revert PRs #2203 and #2244.whitequark2020-07-091-19/+10
| | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* Support logic typed parametersLukasz Dalek2020-07-061-7/+10
| | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-4/+10
|\ | | | | Signed and macro grammar update
| * Parse macro call attached semicolon as empty expressionLukasz Dalek2020-06-261-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * Fix integer signing grammarLukasz Dalek2020-06-261-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit fixes signed/unsigned grammar in parameters as defined in SV LRM A2.2.1. Example of correct parameters: parameter integer signed i = 0; parameter integer unsigned i = 0; Example of incorrect parameters: parameter signed integer i = 0; parameter unsigned integer i = 0; Signed-off-by: Lukasz Dalek <ldalek@antmicro.com> Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Merge pull request #2179 from splhack/static-castclairexen2020-07-012-0/+21
|\ \ | | | | | | Support SystemVerilog Static Cast
| * | static cast: support changing size and signednessKazuki Sakamoto2020-06-192-0/+21
| |/ | | | | | | | | | | | | | | | | Support SystemVerilog Static Cast - size - signedness - (type is not supposted yet) Fix #535
* | Merge pull request #2188 from antmicro/missing-operatorswhitequark2020-06-262-2/+49
|\ \ | | | | | | Add logic-assignments operators
| * | Support missing sub-assign and and-assign operatorsKamil Rakoczy2020-06-252-2/+21
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Support missing xor-assign operatorLukasz Dalek2020-06-242-1/+10
| | | | | | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
| * | Add plus-assignment operatorKamil Rakoczy2020-06-242-1/+10
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
| * | Add or-assignment operatorKamil Rakoczy2020-06-242-1/+11
| |/ | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Support optional labels at the end of package definitionLukasz Dalek2020-06-241-1/+1
| | | | | | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* | Support optional labels at the end of module definitionLukasz Dalek2020-06-241-1/+1
|/ | | | Signed-off-by: Lukasz Dalek <ldalek@antmicro.com>
* Use C++11 final/override keywords.whitequark2020-06-181-6/+6
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* MSVC does not understand __builtin_unreachableAnonymous Maarten2020-06-171-1/+1
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* MSVC cannot omit operand in conditionalAnonymous Maarten2020-06-171-1/+1
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* Support packed arrays in struct/union.Peter Crozier2020-06-071-5/+5
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* Merge branch 'master' into structPeter Crozier2020-06-032-38/+56
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| * Merge pull request #2033 from boqwxp/cleanup-verilog-lexerwhitequark2020-05-291-6/+5
| |\ | | | | | | verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
| | * verilog: Move lexer location variables from global namespace to ↵Alberto Gonzalez2020-05-061-6/+5
| | | | | | | | | | | | `VERILOG_FRONTEND` namespace.
| * | Silence spurious warning in Verilog lexer when compiling with GCCRupert Swarbrick2020-05-261-1/+3
| | | | | | | | | | | | | | | | | | | | | The chosen value shouldn't have any effect. I considered something clearly wrong like -1, but there's no checking inside the generated lexer, and I suspect this will cause even weirder bugs if triggered than just setting it to INITIAL.
| * | verilog: move attr from simple_behav_stmt to its children to attachEddie Hung2020-05-251-13/+17
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| * | verilog: do not warn for attributes on null statementsEddie Hung2020-05-251-2/+0
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| * | verilog: handle empty generate statement by removing gen_stmt_or_null...Eddie Hung2020-05-251-7/+8
| | | | | | | | | | | | | | | ... rule which causes a s/r conflict. Now we get an empty genblock, which should be okay.
| * | verilog: fix #2037 by permitting (and freeing) attributes on null stmtEddie Hung2020-05-251-1/+5
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| * | Merge pull request #2057 from YosysHQ/eddie/fix_task_attrEddie Hung2020-05-211-11/+9
| |\ \ | | | | | | | | verilog: support attributes before (not after) task identifier (but 13 s/r conflicts)
| | * | Update frontends/verilog/verilog_parser.yEddie Hung2020-05-211-1/+1
| | | | | | | | | | | | Co-authored-by: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
| | * | verilog: attributes before task enable (but 13 s/r conflicts)Eddie Hung2020-05-141-10/+8
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