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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-07-10 14:56:14 +0200 |
|---|---|---|
| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-07-10 15:03:53 +0200 |
| commit | d77b3305d83f6877f2177daecab658067659f4ce (patch) | |
| tree | 1863390e2ae5805c6a5e59c49ddb9c56c6e4ecb5 /frontends/verilog | |
| parent | 0ffaddee5e6422c74fd002f9b1272cfe40839a13 (diff) | |
| download | yosys-d77b3305d83f6877f2177daecab658067659f4ce.tar.gz yosys-d77b3305d83f6877f2177daecab658067659f4ce.tar.bz2 yosys-d77b3305d83f6877f2177daecab658067659f4ce.zip | |
Fix S/R conflicts
This commit fixes S/R conflicts introduced by commit 6f9be93.
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 1c86c7895..b9e721415 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -742,12 +742,13 @@ module_body: module_body module_body_stmt | /* the following line makes the generate..endgenrate keywords optional */ module_body gen_stmt | + module_body ';' | /* empty */; module_body_stmt: task_func_decl | specify_block | param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | enum_decl | struct_decl | - always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block | /* empty statement */ ';'; + always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; checker_decl: TOK_CHECKER TOK_ID ';' { |